WEDPN4M64V

White Electronic Designs 4Mx64 Synchronous DRAM FEATURES High Frequency = 100, 125, 133MHz Package: 219 Plastic Ball Grid Array (PBGA), 21 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 4M x 64 User Configurable as 2x4Mx32 or 4x4Mx16 Weight: WEDPN4M64V-XBX - 2 grams typical WEDPN4M64V-XBX GENERAL DESCRIPTION The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 4 chips containing 67,108,864 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column l...