DatasheetsPDF.com

WEDPN4M72V Dataheets PDF



Part Number WEDPN4M72V
Manufacturers White Electronic Designs
Logo White Electronic Designs
Description 4M x 72 SDRAM
Datasheet WEDPN4M72V DatasheetWEDPN4M72V Datasheet (PDF)

White Electronic Designs 4Mx72 Synchronous DRAM* FEATURES            Package:  219 Plastic Ball Grid Array (PBGA), 25 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Orga.

  WEDPN4M72V   WEDPN4M72V


Document
White Electronic Designs 4Mx72 Synchronous DRAM* FEATURES            Package:  219 Plastic Ball Grid Array (PBGA), 25 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 4M x 72 Weight: WEDPN4M72V-XBX - 2 grams typical High Frequency = 100, 125MHz WEDPN4M72V-XBX GENERAL DESCRIPTION The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 5 chips containing 67,108,864 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.    60% SPACE SAVINGS Reduced part count Reduced I/O count  19% I/O Reduction w w    w Lower inductance and capacitance for low noise performance Suitable for hi-reliability applications Upgradeable to 8M x 72 density with same footprint (contact factory for information) * This product is Not Recommended for New Designs, refer to WEDPN4M72V-XB2X for new designs. Nata .D Area I/O Count T O 22.3 R The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. Sh Discrete Approach 11.9 11.9 11.9 11.9 ACTUAL SIZE 11.9 54 TSOP ee 54 TSOP 5 x 265mm 2 = 1328mm 2 5 x 54 pins = 270 pins 1 t4 U .c 54 TSOP 54 TSOP 54 TSOP 21 White Electronic Designs WEDPN4M72V-XBX 25 S A V I N G S 60% 19% White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2004 Rev. 15 om 525mm 2 219 Balls White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com www.DataSheet4U.com BENEFITS C E M O Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A011 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. M N E E D * D The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. White Electronic Designs PIN CONFIGURATION TOP VIEW 1 A B C D E F G H J K L M N P R T DQ1 DQ3 DQ6 DQ7 CAS0# CS0# VSS VSS NC NC DQ56 DQ57 DQ60 DQ62 VSS 2 DQ0 DQ2 DQ4 DQ5 DQML0 WE0# RAS0# VSS VSS CKE3 CK3 DQMH3 DQ58 DQ59 DQ61 DQ63 3 DQ14 DQ12 DQ10 DQ8 VCC VCC VCC VCC VCC VCC VCC VCC DQ55 DQ53 DQ51 DQ49 4 DQ15 DQ13 DQ11 DQ9 DQMH0 CK0 CKE0 VCC VCC CS3# CAS3# WE3# DQ54 DQ52 DQ50 DQ48 5 VSS VSS VCC VCC NC NC NC VSS VSS NC RAS3# DQML3 CKE4 DQMH4 NC VSS VCC VCC NC VSS VCC VCC DQ73 DQ75 DQ77 DQ79 CK4 DQ72 DQ74 DQ76 DQ78 CAS4# WE4# RAS4# DQ71 DQ69 DQ67 DQ65 DQ70 DQML4 DQ68 DQ66 DQ64 VCC VSS VSS 6 VSS VSS VCC VCC NC 7 A9 A0 A2 DNU* NC 8 A10 A7 A5 DNU BA0 9 A11 A6 A4 DNU BA1 10 A8 A1 A3 DNU NC 11 VCC VCC VSS VSS NC WEDPN4M72V-XBX 12 VCC VCC VSS VSS NC RAS1# CAS1# VCC VCC NC NC CS4# NC VCC VSS VSS 13 DQ16 DQ18 DQ20 DQ22 DQML1 WE1# CS1# VSS VSS CKE2 CK2 DQMH2 DQ41 DQ43 DQ45 DQ47 14 DQ17 DQ19 DQ21 DQ23 VSS VSS VSS VSS VSS VSS VSS VSS DQ40 DQ42 DQ44 DQ46 15 DQ31 DQ29 DQ27 DQ26 NC DQMH1 NC VCC VCC RAS2# WE2# DQML2 DQ37 DQ36 DQ34 DQ32 16 VSS DQ30 DQ28 DQ25 DQ24 CK1 CKE1 VCC VCC CS2# CAS2# DQ39 DQ38 DQ35 DQ33 VCC NOTE: DNU = Do Not Use, to be left unconnected for future upgrades. * Pin D7 is DNU for 4M x 72, 8M x 72 product, Pin D7 is A12 for 16M x 72 and higher densities. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2004 Rev. 15 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 1 – FUNCTIONAL BLOCK DIAGRAM WE0# RAS 0# CAS 0# WEDPN4M72V-XBX WE# RAS# CAS# A0-11 A0-11 BA0-1 CK0 DQ0 DQ0 BA0-1 CK CKE CS# DQML DQMH U0 CKE0 CS0# DQML0 • • • • • • DQ15 • • • • • • DQ15 WE1# RAS 1# CAS 1# DQMH0 WE# RAS# CAS# A0-11 BA0-1 DQ0 DQ16 CK1 CKE1 CS1# DQML1 DQMH1 CK CKE CS# DQML DQMH U1 • • • • • • DQ15 • • • .


WEDPN4M64V WEDPN4M72V 1603103G


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)