DatasheetsPDF.com

EBD52UC8AKDA Dataheets PDF



Part Number EBD52UC8AKDA
Manufacturers Elpida Memory
Logo Elpida Memory
Description 512MB DDR SDRAM SO DIMM
Datasheet EBD52UC8AKDA DatasheetEBD52UC8AKDA Datasheet (PDF)

PRELIMINARY DATA SHEET 512MB DDR SDRAM SO DIMM EBD52UC8AKDA (64M words × 64 bits, 2 Ranks) Description The EBD52UC8AKDA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and wri.

  EBD52UC8AKDA   EBD52UC8AKDA



Document
PRELIMINARY DATA SHEET 512MB DDR SDRAM SO DIMM EBD52UC8AKDA (64M words × 64 bits, 2 Ranks) Description The EBD52UC8AKDA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TCP on the module board. Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. Features • 200-pin socket type small outline dual in line memory module (SO DIMM)  PCB height: 31.75mm  Lead pitch: 0.6mm • 2.5V power supply • Data rate: 333Mbps/266Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs, outputs and DM are synchronized with DQS • 4 internal banks for concurrent operation (Component) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.5 • Refresh cycles: (8192 refresh cycles /64ms)  7.8µs maximum average periodic refresh interval • 2 variations of refresh  Auto refresh  Self refresh Document No. E0367E20 (Ver. 2.0) Date Published March 2003 (K) Japan URL: http://www.elpida.com Elpida Memory , Inc. 2003 EBD52UC8AKDA Ordering Information Data rate Mbps (max.) 333 266 266 Component JEDEC speed bin (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact pad Mounted devices 256M bits DDR SDRAM TCP*1 Part number EBD52UC8AKDA-6B EBD52UC8AKDA-7A EBD52UC8AKDA-7B Package 200-pin SO DIMM Gold Note: Please refer to 256Mb DDR TSOP product datasheet for electrical characteristics. Pin Configurations Front side 1 pin 39 pin 41 pin 199 pin 2 pin 40 pin 42 pin Back side 200 pin Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Pin name VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin No. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Pin name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC NC VSS CK2 /CK2 VDD CKE1 NC A12 Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Pin name VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 Pin No. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Pin name VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC NC VSS VSS VDD VDD CKE0 NC A11 Preliminary Data Sheet E0367E20 (Ver. 2.0) 2 EBD52UC8AKDA Pin No. 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Pin name A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS Pin No. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Pin name DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin No. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Pin name A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS Pin No. 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Pin name DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC Preliminary Data Sheet E0367E20 (Ver. 2.0) 3 EBD52UC8AKDA Pin Description Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7 DM0 to DM7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS VDDID NC Function Address input Row address Column address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Pow.


EBD51RC4AKFA-E EBD52UC8AKDA EBD52EC8AKFA-5


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)