EBD52UC8AKDA

PRELIMINARY DATA SHEET 512MB DDR SDRAM SO DIMM EBD52UC8AKDA (64M words × 64 bits, 2 Ranks) Description The EBD52UC8AKDA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TCP on the module board. Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. Features 200-pin socket type small outline dual in line memory module (SO DIMM)  PCB height: 31.75mm  Lead pitch: 0.6mm 2.5V power supply Data rate: 333Mbps/266Mbps (max.) 2.5 V (SSTL_2 compatible) I/O Double Data Rate architecture; two data transfers per clock cycle Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver Data inputs, outputs and DM are synchronized with DQS 4 internal banks for concurrent operation (Component) DQS is edge aligned with data for READs; ...