CHD408LVW

CHD408LVS-55,70 CHD408LVW-55,70 Rev 2.2 Jul’03 4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™ LOW-POWER ASYNCHRONOUS SRAM DESCRIPTION The CHD408L is a family of low voltage, low power 4Mbit static RAMs organized as 512K-words by 8-bit, designed with Cascade’s patent pending SuperT-SRAM™ technology, fabricated with low-power 0.18µm process technology. The CHD408LVS is designed specifically for low-power applications such as mobile cellular phones, personal digital assistants and other battery-operated products. CHD408LVS -55,70 is packaged in sTSOP-I packages, with normal and reverse lead-bending. sTSOP-I packages are available in dimensions of 8x12mm and 8x20mm. FEATURES Low power Low active and standby power for hand-held applications. Single power supply. 55ns or 70ns access time 100% compatible with JEDEC asynchronous SRAM. No clocks, no refresh. No timing restrictions. No special power-up sequence requirement. Direct TTL compatibility for all inputs and outputs. High Performance Compatibility Technology Designed with Cascade’s patent pending SuperT-SRAM™ technology. - Fabricated with low-power 0.18µm process technology. Extended temperature range –40 ~ 85°C . PART NAME TABLE & KEY SPEC SUMMARY Max. Access Time @ 2.7V 70ns 55ns Standby Icc Max @ 3.0V 85°C 35 µA 35 µA Active Icc 3.0V 10MHz 8mA 8mA Power Supply Part Name 2.7V ~ 3.6V 3.0V ~ 3.6V CHD408LVx-70 CHD408LVx-55 PART SELECTION TABLE w w Part Name Package Lead Bending w .D CHD408LVS-55,70 8x1...