ICS332

ADVANCE INFORMATION ICS332 QTClock™ Dual Output Clock Features Packaged as 8 pin SOIC Zero ppm synthesis error in many cases Input crystal frequency from 5 to 27 MHz Input clock frequency from 3 to 50 MHz Two output clocks Spread spectrum capability Output clock frequencies up to 200 MHz Duty cycle of 45/55 3.3 V operating voltage (consult ICS for 5V) Advanced, low power CMOS process For one output clock (lowest jitter), use the ICS331. For three output clocks, see the ICS333. For more than three outputs, use the ICS355. Description The ICS332 is a low cost frequency generator that is factory programmable. Using Phase-LockedLoop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal or clock input to produce two output clocks. The chip has one select input that allows the selection of one of two different frequencies stored in memory. The device also has an power down feature that tri states the clock outputs and turns off the PLL when the PDTS pin is taken low. This data sheet is to be used with the one-page programming information for the complete specification on the device. Block Diagram SEL X1/ICLK X2 PDTS (both outputs and PLL) Optional crystal capacitors MDS 332 1 Revision 111000 Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com www.DataSheet4U.com 5-27 MHz crystal or clock w w .D w OTP ROM with PLL Divider Values Crystal Oscillator t a S a e h t e ...