CY3125

5 m o CY3125 .c U ® 4 t Warp CPLD Development Tool for UNIX e e Features h S a at .D w w w VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with the following features: — Designs are portable across multiple devices and/or EDA environments — Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design — Support for functions and libraries facilitating modular design methodology IEEE Standard 1076 and 1164 VHDL synthesis supports: — Enumerated types — Operator overloading — For... Generate statements — Blocking and non-blocking procedural assignments — While loops — Integers Several design entry methods support high-level and low-level design descriptions: — Behavioral VHDL and Verilog (IF...THEN...ELSE; CASE...) — Boolean — Structural Verilog and VHDL DESIGN ENTRY — Integers IEEE Standard 1364 Verilog synthesis supports: — Reduction and conditional operators — Designs can include multiple entry methods (but only one HDL language) in a single design. UltraGen™ Synthesis and Fitting Technology: — Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device. — User-selectable speed and/or area optimization on a block-by-block basis — Perfect communication between synthesis and fitting — Automatic selection of optimal flip-flop type (D type/T type) m o .c U 4 t e e h S a t a .D w w w Functional Descript...