Document
™ t e 8Mb SYNCBURST e h SRAMS
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8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
MT58L512L18D, MT58L256L32D, MT58L256L36D
3.3V VDD, 3.3V I/O, Pipelined, DoubleCycle Deselect
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• • • • • • • • • • • • • • •
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Fast clock and OE# access times Single +3.3V +0.3V/-0.165V power supply (VDD) Separate +3.3V isolated output buffer supply (VDDQ) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications 100-pin TQFP package 165-pin FBGA package Low capacitive bus loading x18, x32, and x36 versions available
100-Pin TQFP**
OPTIONS
• Timing (Access/Cycle/MHz) 3.5ns/6ns/166 MHz 4.0ns/7.5ns/133 MHz 5ns/10ns/100 MHz • Configurations 512K x 18 256K x 32 256K x 36
MARKING
• Packages 100-pin TQFP (2-chip enable) 100-pin TQFP (3-chip enable) 165-pin, 13mm x 15mm FBGA
• Operating Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C)**
Part Number Example
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MT58L512L18D MT58L256L32D MT58L256L36D
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
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165-Pin FBGA
GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version.
MT58L512L18DT-7.5
* A Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/support/index.html. ** Industrial temperature range offered in specific speed grades and configurations. Contact factory for more information.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc.
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8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM 512K x 18
19 SA0, SA1, SA MODE ADV# CLK ADDRESS REGISTER 19 17 19
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SA0-SA1 SA1'
BINARY Q1 COUNTER AND LOGIC CLR Q0
SA0'
ADSC# ADSP# BYTE “b” WRITE REGISTER 9 BYTE “b” WRITE DRIVER 9 512K x 9 x 2 MEMORY ARRAY 9 18 SENSE 18 AMPS
BWb#
OUTPUT 18 REGISTERS
OUTPUT BUFFERS E
18
BWa# BWE# GW# CE# CE2 CE2# OE#
BYTE “a” WRITE REGISTER
9
BYTE “a” WRITE DRIVER
DQs DQPa DQPb
ENABLE REGISTER
18
PIPELINED ENABLE 2
INPUT REGISTERS
FUNCTIONAL BLOCK DIAGRAM 256K x 32/36
18
SA0, SA1, SA
ADDRESS REGISTER
16
SA0-SA1
18
MODE ADV# CLK Q1 BINARY COUNTER SA0' CLR Q0
SA1'
ADSC# ADSP# BWd# BYTE “d” WRITE REGISTER BYTE “c” WRITE REGISTER
9
BYTE “d” WRITE DRIVER BYTE “c” WRITE DRIVER BYTE “b” WRITE DRIVER BYTE “a” WRITE DRIVER
9
BWc#
9
9
256K x 8 x 4 (x32) 256K x 9 x 4 (x36) 36 SENSE AMPS 36
OUTPUT REGISTERS 36
BWb#
BYTE “b” WRITE REGISTER
9
9
MEMORY ARRAY
OUTPUT BUFFERS E
DQs DQPa
36
DQPd
BWa# BWE# GW# CE# CE2 CE2# OE#
BYTE “a” WRITE REGISTER
9
9
ENABLE REGISTER
36
PIPELINED ENABLE 4
INPUT REGISTERS
NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams for detailed information.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This all.