Configuration PROMs. XC17S40XL Datasheet

XC17S40XL Datasheet PDF, Equivalent


Part Number

XC17S40XL

Description

(XC17S00/XL Series) One-Time Programmable Configuration PROMs

Manufacture

Xilinx

Total Page 11 Pages
PDF Download
Download XC17S40XL Datasheet PDF


XC17S40XL Datasheet
Product Obsolete or Under Obsolescence
X-Ref Target - Figure 0
R Spartan/XL Family One-Time Programmable
Configuration PROMs (XC17S00/XL)
DS030 (v1.12) June 20, 2008
Product Specification
Features
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan®, and Spartan-XL FPGAs
Simple interface to the Spartan device requires only
one user I/O pin
Programmable reset polarity (active High or active Low)
Low-power CMOS floating-gate process
Available in 5V and 3.3V versions
Available in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC packages
Programming support by leading programmer
manufacturers
Lead-free (RoHS-compliant) packaging available
Design support using the Xilinx® Alliance and
Foundation™ series software packages
Guaranteed 20 year life data retention
Introduction
The Spartan family of PROMs provides an easy-to-use,
cost-effective method for storing Spartan device
configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
FPGA PROM. A short access time after the rising clock
edge, data appears on the PROM DATA output pin that is
connected to the Spartan device DIN pin. The Spartan
device generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When a Spartan device is in Slave Serial mode, the
PROM and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
Spartan FPGA
XCS05
XCS05XL
XCS10
XCS10XL
XCS20
XCS20XL
XCS30
XCS30XL
XCS40
XCS40XL
XC2S50(1)
XC2S100(1)
XC2S150(1)
Configuration Bits
53,984
54,544
95,008
95,752
178,144
179,160
247,968
249,168
329,312
330,696
559,200
781,216
1,040,096
Notes:
1. For new Spartan-II FPGA designs, it is recommended to use the 17S00A family.
Compatible Spartan PROM
XC17S05
XC17S05XL
XC17S10
XC17S10XL
XC17S20
XC17S20XL
XC17S30
XC17S30XL
XC17S40
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
© Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS030 (v1.12) June 20, 2008
Product Specification
www.xilinx.com
1

XC17S40XL Datasheet
R ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)
Pin Description
Pins not listed are in Table 1 are "no connects."
Table 1: Spartan PROM Pinouts
Pin Name
8-pin
PDIP (PD8) and
VOIC/TSOP (VO8)
DATA
1
CLK 2
RESET/OE
(OE/RESET)
3
CE
GND
VCC
4
5
7, 8
20-pin
SOIC
(SO20)
1
3
8
10
11
18, 20
Pin Description
Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to be either
active High or active Low.
Each rising edge on the CLK input increments the internal address counter, if both
CE and OE are active.
When High, this input holds the address counter reset and puts the DATA output
in a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin
as RESET/OE, although the opposite polarity is possible on all devices. When
RESET is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the preferred option is active Low RESET, because it can
be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
When High, this pin disables the internal address counter, puts the DATA output
in a high-impedance state, and forces the device into low-ICC standby mode.
GND is the ground connection.
The VCC pins are to be connected to the positive voltage supply.
Pinout Diagrams
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
1
2
3
4
5 SO20
6 Top
7 View
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
DS030_04_110102
DATA(D0)
CLK
OE/RESET
CE
18
2 PD8/PDG8 7
SOG8
3 VO8/VOG8 6
Top View
45
VCC
VCC
NC
GND
DS030_05_060508
DS030 (v1.12) June 20, 2008
Product Specification
www.xilinx.com
2


Features Datasheet pdf Product Obsolete or Under Obsolescence X -Ref Target - Figure 0 R Spartan/XL Fam ily One-Time Programmable Configuration PROMs (XC17S00/XL) DS030 (v1.12) June 20, 2008 Product Specification Featu res • Configuration one-time programm able (OTP) read-only memory designed to store configuration bitstreams for Spa rtan®, and Spartan-XL FPGAs • Simple interface to the Spartan device requir es only one user I/O pin • Programmab le reset polarity (active High or activ e Low) • Low-power CMOS floating-gate process • Available in 5V and 3.3V v ersions • Available in compact plast ic 8-pin DIP, 8-pin VOIC, or 20-pin SOI C packages • Programming support by l eading programmer manufacturers • Lea d-free (RoHS-compliant) packaging avail able • Design support using the Xilin x® Alliance and Foundation™ series s oftware packages • Guaranteed 20 year life data retention Introduction The Spartan family of PROMs provides an eas y-to-use, cost-effective method for storing Spartan device conf.
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