Document
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L3M Device
Level 3 Mapper TXC-03452B DATA SHEET DESCRIPTION
The L3M maps a DS3 line signal into an STM-1 TUG-3 or STS-3/ STS-1 SPE or STS-1 SPE SDH/SONET signal. An E3 line signal is mapped into an STM-1 TUG-3 signal only. The L3M provides a TUG-3 formatted signal for STM-1 operation, or an STS SPE for STS-3 or STS-1 operation. The SDH/SONET signal is transmitted via an add bus with timing derived from the drop side, add side or from external timing (STS-1 only). An option is provided to generate the A1, A2 framing pattern, C1 byte and H1, H2 pointer towards the add bus when external timing mode is selected.
APPLICATIONS
• Add/drop multiplexers
• Digital cross-connect systems • Broadband switching systems • Transmission equipment
SDH/SONET SIDE
“O”-Bits I/O
Ext Alarms
Control
Microprocessor Interface
LINE SIDE
Add Bus
L3M
Level 3 Mapper TXC-03452B
Drop Bus
POH I/O
VCXO Boundary Alarm Port I/O Scan
U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096 U.S. and/or foreign patents issued or pending Copyright 2001 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation
TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
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NRZ, Rail Input NRZ Clock, Data (Monitor) NRZ, Rail Output
Document Number: TXC-03452B-MB Ed. 6, April 2001
•
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
• Maps DS3 (44.736 Mbit/s) or E3 (34.368 Mbit/s) line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 SPE or STS-1 SPE - E3 to/from STM-1/TUG-3 only • SDH/SONET bus access: - Drop/add data byte access (with clock, C1J1, SPE, and parity) - Add bus interface timing derived from drop bus, add bus, or external timing • Path overhead byte processing: - Microprocessor or external interface - B3 generation and detection with test mask - B3 performance counter (16-bit) and block error counter (8-bit) - C2 mismatch and unequipped detection - G1 processing - FEBE count by block or bits (16-bit counter) • Microprocessor access: - Motorola or Intel compatible (selected via a lead) - Hardware/software interrupt capability • Line Interface - Transmit and receive NRZ or rail operation with split operation capability • Testing functions: - SONET, facility, or line loopback - Transmit and receive 215-1 or 223-1 generators and shared analyzer - Boundary scan capability (IEEE 1149.1) • 144-lead plastic quad flat package (PQFP) or 208-lead plastic ball grid array package (PBGA)
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Individual POH bytes for the transmitted SDH/SONET signal are mapped from the L3M memory map or an external interface. An option is provided to generate an unequipped status or TUG-3 path AIS signal. External accesses are provided for the communications channel “O”-bits and alarms for ring operation. The received signal is desynchronized from drop bus STM-1/TUG-3, STS-3/STS-1 SPE, or STS-1 signals. Internal pointer processing is performed for the TUG-3 signal. All POH bytes are provided for the microprocessor.
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TABLE OF CONTENTS
Section
L3M TXC-03452B
Page
List of Figures ....................................................................................................... 3 Block Diagram ..................................................................................................... 5 Block Diagram Description .................................................................................. 6 Lead Diagrams .................................................................................................. 11 Lead Descriptions ............................................................................................. 13 Absolute Maximum Ratings and Environmental Limitations ............................. 24 Thermal Characteristics .................................................................................... 24 Power Requirements ......................................................................................... 24 Input, Output and Input/Output Parameters ...................................................... 25 Timing Characteristics ....................................................................................... 27 Operation .......................................................................................................... 49 L3M Power-Up Reset Sequence ................................................................ 49 PLL Filter Connection to VCXO .................................................................. 51 Testing ........................................................................................................ 53 Boundary Scan ..........................................................................