DP8420A

DP8420A 21A 22A microCMOS Programmable 256k 1M 4M Dynamic RAM Controller Drivers July 1992 DP8420A 21A 22A microCMOS Programmable 256k 1M 4M Dynamic RAM Controller Drivers General Description The DP8420A 21A 22A dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420A 21A 22A generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge An additional feature of the DP8422A is two access ports to simplify dual accessing Arbitration among these ports and refresh is done on chip of Pins (PLCC) 68 68 84 of Address Outputs 9 10 11 Features Y Y Y Y Y Y Y Y Y On chip high precision delay line to guarantee critical DRAM access timing parameters microCMOS process for low power High capacitance drivers for RAS CAS WE and DRAM address on chip On chip support for nibble page and static column DRAMs Byte enable signals on chip allow byte writing in a word size up to 32 bits wi...