HY5DU56822CF

w w w .D a t a e h S et 4U . m o c HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F 256M DDR SDRAM HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F w w w .D t a S a e h t e U 4 .c m o This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ Nov. 2003 1 w w w .D at h S a t e e 4U . m o c HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F Revision History Revision No. 0.1 History Define Preliminary Specification Draft Date Nov. 2003 Remark Rev. 0.1 / Nov. 2003 2 HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F DESCRIPTION PRELIMINARY The Hynix HY5DU56422 and HY5DU56822 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs ar...