HYB39S64400

HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 64 MBit Synchronous DRAM High Performance: -8 fCKmax. tCK3 tAC3 tCK2 tAC2 125 8 6 10 6 -8B 100 10 6 12 7 -10 100 10 7 15 8 Units MHz ns ns ns ns Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 refresh cycles / 64 ms Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface version Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) -8 version for PC100 2-2-2 applications -8B version for PC100 3-2-3 applications Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperature Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 full page (optional) for sequential wrap around The HYB39S64400/800/160AT are four bank Synchronous DRAM’s organized as 4 banks x 4MBit x4, 4 banks x 2MBit x8 and 4 banks x 1Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’ advanced quarter micron 64MBit DRAM process technology. The device is designed to comply with all JEDE...