DatasheetsPDF.com

FAS366U Dataheets PDF



Part Number FAS366U
Manufacturers QLogic
Logo QLogic
Description Fast Architecture SCSI Precossor
Datasheet FAS366U DatasheetFAS366U Datasheet (PDF)

w w a D . w e e FAS366U h SFast Architecture SCSI Processor a t Data Sheet H H H H H H H H H H H Support for hot plugging Target and initiator block transfer sequences Bus idle timer Split–bus architecture Pipelined command structure On–chip, single–ended SCSI transceivers (48–mA drivers) Initiator and target roles Active negation 16–bit recommand counter Differential mode SCSI bus reset watchdog timer U 4 t m o .c QLogic Corporation Features H Compliance with ANSI draft Fast–20 standard H.

  FAS366U   FAS366U



Document
w w a D . w e e FAS366U h SFast Architecture SCSI Processor a t Data Sheet H H H H H H H H H H H Support for hot plugging Target and initiator block transfer sequences Bus idle timer Split–bus architecture Pipelined command structure On–chip, single–ended SCSI transceivers (48–mA drivers) Initiator and target roles Active negation 16–bit recommand counter Differential mode SCSI bus reset watchdog timer U 4 t m o .c QLogic Corporation Features H Compliance with ANSI draft Fast–20 standard H Compliance with ANSI X3T10/855D SCSI–3 H Compliance with ANSI SCSI configured H Sustained SCSI data transfer rates of up to: h 40 Mbytes/sec synchronous (ultra and wide H Synchronous DMA timing; DMA speed of 50 Mbytes/sec deassertion control automatically (SCAM) protocol levels 1 and 2 parallel interface (SPI) standard h 14 Mbytes/sec asynchronous (wide SCSI) SCSI) H REQ and ACK programmable assertion and DB BUS w PAD BUS w .D w t a S a e h t e U 4 .c m o SCSI DATA PARITY (2) DATA (16) BLOCK REGISTERS FIFO COMMAND RECOMMAND COUNTER TRANSFER COUNT SEL/RESEL BUS ID SEL/RESEL TIMEOUT TRANSFER COUNTER INTERRUPT STATUS SEQUENCERS SEQUENCE STEP SYNC PERIOD SYNC OFFSET/ SYNC ASSERT/ SYNC DEASSERT CLOCK CONVERSION CONFIGURATION TEST (SCAM) SCSI CONTROL Figure 1. FAS366U Block Diagram 53366–580–01 B w w w .D a S a t e e h U 4 t m o .c FAS366U 1 QLogic Corporation Product Description The FAS366U is a new addition to the QLogic fast architecture SCSI processor (FAS) chip family. The FAS366U supports advanced SCSI–3 options including ultra SCSI synchronous transfers. Also included is the advanced SCAM level 2 SCSI controller core. The FAS366U is a single–chip controller for use in host and peripheral applications. It is firmware and pin–out compatible with the QLogic FAS366 chip. The FAS366U block diagram is shown in figure 1. The FAS366U implements QLogic’s new SCSI target and initiator block transfer sequences. The block sequences reduce firmware overhead and are composed of the following new commands: Target Block Sequence (including the bus idle timer), Initiator Block Sequence, Load/Unload Block Registers sequences, Abort Block Sequence, and Disconnect Abort Block Sequence. The FAS366U supports both single–ended and differential mode SCSI operations and operates in initiator and target roles. The FAS366U has been optimized for interaction with a DMA controller and the controlling microprocessor. The versatile split–bus architecture supports various microprocessor and DMA bus configurations. A separate 8–bit microprocessor bus (PAD) provides access to all internal registers, and a 16–bit DMA bus (DB) provides a path for DMA transfers through the FIFO. Each bus is protected by a parity bit (byte–wide parity) to improve data integrity. During data transfer, the microprocessor has instant access to status and has the ability to execute commands. drivers onto the DMA bus. The chip select role of DACK helps support the burst timin.


HCPL-4562 FAS366U FAS368M


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)