AN9762 Manual Datasheet

AN9762 Datasheet, PDF, Equivalent


Part Number

AN9762

Description

HI5767EVAL2 Evaluation Board Users Manual

Manufacture

intersi

Total Page 16 Pages
Datasheet
Download AN9762 Datasheet


AN9762
HI5767EVAL2 Evaluation Board User’s Manual
TM
.comApplication Note
January 1999
AN9762
et4UDescription
heThe HI5767EVAL2 evaluation board allows the circuit
Sdesigner to evaluate the performance of the Intersil HI5767
tamonolithic 10-bit 20/40/60MSPS analog-to-digital converter
a(ADC). As shown in the Evaluation Board Functional Block
.DDiagram, the evaluation board includes sample clock
generation circuitry, a single-ended to differential analog
winput RF transformer configuration, an on board external
wvariable reference voltage generator and a digital data
woutput header/connector. The digital data outputs are
mconveniently provided for easy interfacing to a ribbon
connector or logic probes. In addition, the evaluation board
oincludes some prototyping area for the addition of user
designed custom interfaces or circuits.
.cThe sample clock generator circuit accepts the external
sampling signal through an SMA type RF connector, J2.
UThis input is AC-coupled and terminated in 50allowing for
connection to most laboratory signal generators. In
t4addition, the duty cycle of the clock driving the A/D
eEvaluation Board Functional Block Diagram
eSAMPLE
hCLOCK
INPUT
J2
50+5VD
BIAS
TEE
ataS1.2V
BANDGAP
VOLTAGE
.DREFERENCE
ANALOG
wINPUT
J1
VAR
GAIN
RF
TRANSFORMER
+2.5V
ww .comDGND AGND
U+5VD +5VA -5VA
converter is adjustable by way of a potentiometer. This
allows the effects of sample clock duty cycle on the HI5767
to be observed.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input RF transformer. This input is
AC-coupled and terminated in 50allowing for connection
to most laboratory signal generators.
The converters’ digital data outputs along with two phases of
the sample clock (CLK and CLK) are provided at the output
header/connector. With this output configuration the digital
data output transitions seen at the I/O header/connector are
essentially time aligned with the rising edge of the sampling
clock (CLK) or the falling edge of the out of phase sampling
clock (CLK).
Refer to the component layout and the evaluation board
electrical schematic for the following discussions.
CLK
VREFIN
VREF OUT
VIN+
D0-D9
VIN-
HI5767
10
CLK
CLOCK
OUT
CLK
DIGITAL
DATA
OUT
(D0 - D9)
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AN9762
Application Note 9762
External Reference Voltage Generator,
VREFOUT and VREFiN
The HI5767 has an internal reference voltage generator,
therefore no external reference voltage is required. The
evaluation board, however, offers the ability to use the
converters’ internal reference voltage, VREFOUT, or the on
board external variable reference voltage generator.
The external variable reference voltage circuitry is
implemented using the Intersil ICL8069 low voltage, 1.2V,
bandgap reference (D1) sourcing a non-inverting variable
gain operational amplifier circuit based on the Intersil
HA5127 ultra-low noise precision operational amplifier (U1).
Potentiometer VR1 is used to adjust the output voltage level
of this external voltage reference. With this the user is able
to observe the effects of reference voltage variations on the
converters performance. Turning VR1 in a clockwise (CW)
direction will decrease the external reference voltage while
turning VR1 in a counterclockwise (CCW) direction will
decrease the external reference voltage.
Selection of the reference voltage to be used by the
converter is accomplished by placing the P3 header jumper
across the appropriate pins. The converters’ internal
reference voltage generator, VREFOUT, must be connected
to VREFIN when using the converters internal reference and
is selected by placing the P3 header jumper across P3-2 and
P3-3. Alternately, if it is desired to use the on board external
variable reference voltage generator, selection of this option
is done by placing the P3 header jumper across P3-1 and
P3-2. See Appendix A, Board Layout for the location of the
P3 reference voltage selection header.
Analog Input
The fully differential analog input of the HI5767 A/D can be
configured in various ways depending on the signal source
and the required level of performance.
Differential Analog Input Configuration
A fully differential connection (Figure 1) will yield the best
performance from the HI5767 A/D converter. Since the
HI5767 is powered off a single +5V supply, the analog input
must be biased so it lies within the analog input common
mode voltage range of 0.25V to 4.75V. Figure 2 illustrates
the differential analog input common mode voltage, VDC,
VIN VIN+
HI5767
VDC
-VIN
VIN -
FIGURE 1. AC COUPLED DIFFERENTIAL INPUT
range that the converter will accommodate. The
performance of the converter does not change significantly
with the value of the analog input common mode voltage.
+5V VIN+
0.5VP-P
VIN-
VDC = 4.75V
+5V
FIGURE 2A.
VIN+
0.5VP-P
VIN-
0.25V < VDC < 4.75V
FIGURE 2B.
VIN+
0V
0.5VP-P
VIN-
VDC = 0.25V
0V
FIGURE 2C.
FIGURE 2. DIFFERENTIAL ANALOG INPUT COMMON MODE
VOLTAGE RANGE
A DC bias voltage source, VDC, equal to 3.0V (typical), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes an
excellent DC bias source and stays well within the analog input
common mode voltage range over temperature.
For the AC coupled differential input (Figure 1) and with
VREFIN connected to VREFOUT, full scale is achieved when
the VIN and -VIN input signals are 0.5VP-P, with -VIN being
180 degrees out of phase with VIN. The converter will be at
positive full scale when the VIN+ input is at VDC + 0.25V and
the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V).
Conversely, the converter will be at negative full scale when
the VIN+ input is equal to VDC - 0.25V and VIN- is at
VDC + 0.25V (VIN+ - VIN- = -0.5V).
It should be noted that overdriving the analog input beyond
the ±0.5V fullscale input voltage range will not damage the
converter as long as the overdrive voltage stays within the
converters analog supply voltages. In the event of an
overdrive condition the converter will recover within one
sample clock cycle.
A single-ended input will give better overall system
performance if it is first converted to differential before
driving the HI5767. An RF transformer can be connected to
the HI5767 input to provide the single-ended to differential
conversion. The particular transformer used will depend on
the input voltage level, the impedance desired, and the input
frequency range. The transformer will tend to have a
bandpass response resulting in low and high frequency
3-2


Features HI5767EVAL2 Evaluation Board User’s Ma nual TM Description w The HI5767EVAL 2 evaluation board allows the circuit d esigner to evaluate the performance of the Intersil HI5767 monolithic 10-bit 2 0/40/60MSPS analog-to-digital converter (ADC). As shown in the Evaluation Boar d Functional Block Diagram, the evaluat ion board includes sample clock generat ion circuitry, a single-ended to differ ential analog input RF transformer conf iguration, an on board external variabl e reference voltage generator and a dig ital data output header/connector. The digital data outputs are conveniently p rovided for easy interfacing to a ribbo n connector or logic probes. In additio n, the evaluation board includes some p rototyping area for the addition of use r designed custom interfaces or circuit s. w at .D w aS e e h U 4 t m o N ote c .Application January 1999 AN976 2 converter is adjustable by way of a potentiometer. This allows the effects of sample clock duty cycle on the HI5767 to be observed. The anal.
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