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ICS2595 Dataheets PDF



Part Number ICS2595
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description User-Programmable Dual High-Performance Clock Generator
Datasheet ICS2595 DatasheetICS2595 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS2595 Not recommended for new designs User-Programmable Dual High-Performance Clock Generator Description The ICS2595 is a dual-PLL (phase-locked loop) clock generator specifically designed for high-resolution, highrefresh rate, video applications. The video PLL generates any of 16 pre-programmed frequencies through selection of the address lines FS0-FS3. Similarly, the auxiliary PLL can generate any one of four pre-programmed frequencies via the MS0 & MS1 li.

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Integrated Circuit Systems, Inc. ICS2595 Not recommended for new designs User-Programmable Dual High-Performance Clock Generator Description The ICS2595 is a dual-PLL (phase-locked loop) clock generator specifically designed for high-resolution, highrefresh rate, video applications. The video PLL generates any of 16 pre-programmed frequencies through selection of the address lines FS0-FS3. Similarly, the auxiliary PLL can generate any one of four pre-programmed frequencies via the MS0 & MS1 lines. A unique feature of the ICS2595 is the ability to redefine frequency selections in both the VCLK and MCLK synthesizers after power-up. This permits complete set-up of the frequency table upon system initialization. Features • • • • • • Advanced ICS monolithic phase-locked loop technology for extremely low jitter Supports high-resolution graphics - VCLK output to 145 MHz Completely integrated - requires only external crystal (or reference frequency and decoupling) Power-down modes support portable computing Sixteen selectable VCLK frequencies (all user re-programmable) Four selectable MCLK frequencies (all user re-programmable) Applications • • PC Graphics VGA/Supper VGA/XGA Applications Block Diagram Pin Configuration 20-Pin DIP or SOIC ICS2595 RevB 3/2/00 ICS2595 Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 9 10,14,16 11 12 13,20 15 17 18 19 PIN NAME X1 X2 EXTFREQ FS0 FS1 STROBE FS2 FS3 MS0 GND MS1 MCLK VDD VAA RESERVED REFCLK VCLK TYPE IN OUT IN IN IN IN IN IN IN PWR IN OUT PWR PWR N/C OUT OUT DESCRIPTION Quartz crystal connection 1/Reference Frequency Input Quartz crystal connection2 External Frequency Input VCLK PLL Frequency Select LSB VCLK PLL Frequency Select Bit Control for Latch of VCLK Select its (FS0-FS3) VCLK PLL Frequency Select Bit VCLK PLL Frequency Select MSB MCLK PLL Frequency Select LSB Device Ground. All pins must be connected MCLK PLL Frequency Select MSB MCLK Frequency Output Output Stage VDD. All pins must be connected Synthesizer VDD Must be connected to GND Buffered Referenced Clock Output VCLK Frequency Output 2 ICS2595 Digital Inputs The FS0-FS3 pins and the STROBE pin are used to select the desired operating frequency of the VCLK output from the 16 pre-programmed/user-programmed selections in the ICS2595. These pins are also used to load new frequency data into the registers. The standard interface for the ICS2595 matches the interface of the industry standard ICS2494. That is, the FS0-FS3 inputs access the device internals transparently when the STROBE pin is high. The digital interface for the ICS2595 (i.e. the FS0-FS3 inputs) may be optionally configured for edge-triggered or level-activated operation of the STROBE pin. Example timing requirements for each of the four options are shown in Figure 1. The programming sequence has been designed in such a way that STROBE pin need not be used (as in situations where the device is connected to the frequency select port of some VGA chips). Because the same pins are used for both VCLK frequency selection and re-programming the device frequency table, a specific procedure must be observed for selection between these modes. Device programming is accomplished by Table 1: Programming Sequence Nibble 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 FS0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS2 0 1 START bit (must be "0") " R/W* control bit (must be "0") " LO (location LSB) " L1 " L2 " L3 " L4 (location MSB) " N 0 (feedback LSB " N1 " N2 " N3 " N4 " N5 " N6 " N 7(feedback MSB) " EXTFREQ (select if "1") " D0 (post- divder MSB) " D1 (post- divder MSB) " STO P1 bit (must be "1") " STO P2 bit (must be '1") " FS3 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCLK Output Frequency Selection To change the VCLK output frequency, simply write the appropriate data to the ICS2595 FS inputs. The synthesizer will output the new frequency programmed into that location after a brief delay (see time-out specifications). Upon device power-up, the selected frequency will be the frequency pre-programmed into address 0 until a device write is performed. MCLK Output Frequency Selection The MS0-MS1 pins are used to directly select the desired operating frequency of the MCLK output from the four pre-programmed/user-programmed selections in the ICS2595. These inputs are not latched, nor are they involved with memory programming operations. Programming Mode Selection In order to ensure that reliable programming under all circumstances, we require that two "nibble" writes be added to the beginning of the programming sequence that was previously specified. The new sequence is shown in Table 1. Note that the FS3 data is "0" for these first two writes. 3 executing a "programming sequence". The latched FS2 input functions as a.


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