ICS2509C

Integrated Circuit Systems, Inc. ICS2509C 3.3V Phase-Lock Loop Clock Driver General Description The ICS2509C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2509C operates at 3.3V VCC and drives up to nine clock loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN. Each bank of outputs can be enabled or disabled separately via control (OEA and OEB) inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN; when the OE inputs are low, the outputs are disabled to the logic low state. The ICS2509C does not require external RC filter components. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The buffer mode shuts off the PLL and connects the input directly to the output buffer. This buffer mode, the ICS2509C can be use as low skew fanout clock buffer device. The ICS2509C comes in 24 pin 173mil Thin Shrink Small-Outline package (TSSOP) package. Features Meets or exceeds PC133 registered DIMM specification 1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of five and one bank of four outputs Separate outpu...