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IN82C55 Dataheets PDF



Part Number IN82C55
Manufacturers IK Semiconductor
Logo IK Semiconductor
Description Promrammable Periphral Interface
Datasheet IN82C55 DatasheetIN82C55 Datasheet (PDF)

CHMOS PROGRAMMABLE PERIPHERAL INTERFACE he The Integral IN82C55AN is a high-performance, CHMOS version of the industry standard IN82C55AN general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. e U 4 t m o .c TECHNICAL DATA IN82C55 w MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs .

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CHMOS PROGRAMMABLE PERIPHERAL INTERFACE he The Integral IN82C55AN is a high-performance, CHMOS version of the industry standard IN82C55AN general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. e U 4 t m o .c TECHNICAL DATA IN82C55 w MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or w In outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bidirectional bus configuration. FEATURES • • • • • • • • • • a D . w S a t Compatible with all Intel and Most Other Microprocessors High Speed, «Zero Wait State» Operation with 8MHz 8086/88 and 80186/188 24 Programmable I/O Pins Low Power CHMOS Completely TTL Compatible Control Word Read-Back Capability Direct Bit Set/Reset Capability 2.5mA DC Drive Capability on all I/O Port Outputs Available in 40-Pin DIP Available in EXPRESS ƒ Standard Temperature Range ƒ Extended Temperature Range ƒ GROUP A CONTROL D7-D0 DATA BUS BUFFER w w w t a .D S a e h PA7-PA0 PC7-PC4 U 4 t e PA3 PA2 PA1 PA0 RD CS VSS A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 .c m o GROUP A PORT A (8) GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4) 8 BIT INTERNAL DATA BUS PC3-PC0 RD WR A1 A0 Reset READ/ WRITE CONTROL LOGIC GROUP B CONTROL GROUP B PORT B (8) PB7-PB0 CS Figure 1 w w w a D . Figure 2 1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11 12 13 14 15 16 17 18 19 20 S a t 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 e e h U 4 t PA4 PA5 PA6 PA7 WR Reset D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3 m o .c 1 IN82C55A Symbol PA3-0 RD CS Pin number 1-4 5 6 7 8-9 Type I/O I I Name and Function PORT A, PINS 0-3: Lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch. READ CONTROL: This input is low during CPU read operations. CHIP SELECT: A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise. System Ground. ADDRESS: These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers. Input Operation (Read) A1 A0 CS WR RD Port A - Data Bus 0 0 0 1 0 Port B - Data Bus 0 1 0 1 0 Port C - Data Bus 1 0 0 1 0 Control Word - Data Bus 1 1 0 1 0 Output Operation (Write) GND A1-0 I 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 Data Bus - Port A Data Bus - Port B Data Bus - Port C Data Bus – Control Disable Function PC7-4 10-13 I/O PC0-3 PB0-7 VCC D7-0 RESET WR PA7-4 14-17 18-25 26 27-34 35 36 37-40 I/O I/O I/O I I I/O Data Bus-3-State x x x x 1 Data Bus-3-State x x 1 1 0 PORT C, PINS 4-7: Upper nibble of an 8-bit data output latch/buffer and an 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. PORT C, PINS 0-3: Lower nibble of Port C. PORT B, PINS 0-7: An 8-bit data output latch/buffer and an 8-bit data input buffer SYSTEM POWER: +5V Power Supply DATA BUS: Bi-directional, tri-state data bus lines, connected to system data bus RESET: A high on this input clears the control register and all ports are set to the input mode WRITE CONTROL: This input is low during CPU write operations PORT A PINS 4-7: Upper nibble of an 8-bit data output latch/buffer and an 8-bit data input latch 2 IN82C55A IN82C55AN FUNCTIONAL DESCRIPTION General The IN82C55AN is a programmable peripheral interface device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configuration of the IN82C55AN is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to interface the IN82C55AN to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the IN82C55AN. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the func.


ILX232 IN82C55 INF8574


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