IS42S16400

IS42S8800/IS42S8800L m IS42S16400/IS42S16400L o c . 2(1)M Words x U 8(16) Bits x 4 Banks (64-MBIT) 4 t DYNAMIC RAM SYNCHRONOUS e e FEATURES h DESCRIPTION S The IS42S8800 and IS42S16400 are high-speed 67, • Single 3.3V a (± 0.3V) power supply t 108,864-bit synchronous dynamic random-access • High speed clock cycle time -7: 133MHz<3-3-3>, a moeories, organized as 2,097,152 x 8 x 4 and 1,048, -8: . 100MHz<2-2-2> D 576 x 16 x 4 (word x bit x bank), respectively. • Fully synchronous operation referenced to clock w wrising edge The synchronous DRAMs achieved high-speed data w• Possible to assert random column access in transfer using the pipeline architecture and clock • • • • • • • • • • • • every cycle Quad internal banks contorlled by A12 & A13 (Bank Select) Byte control by LDQM and UDQM for IS42S16400 Programmable Wrap sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable /CAS latency (2 and 3) Automatic precharge and controlled precharge CBR (Auto) refresh and self refresh X8, X16 organization LVTTL compatible inputs and outputs 4,096 refresh cycles / 64ms Burst termination by Burst stop and Precharge command Package 400mil 54-pin TSOP-2 frequency up to 133MHz for -7. All input and outputs are synchronized with the postive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are pack-aged in 54-pin TSOP-2. w w w .D t a S a e h t e U 4 .c m o ICSI reserves the right to mak...