MT4LC16M4H9

16 MEG x 4 EDO DRAM DRAM FEATURES Single +3.3V ±0.3V power supply Industry-standard x4 pinout, timing, functions, and packages 12 row, 12 column addresses (H9) or 13 row, 11 column addresses (G3) High-performance CMOS silicon-gate process All inputs, outputs and clocks are LVTTL-compatible Extended Data-Out (EDO) PAGE MODE access Optional self refresh (S) for low-power data retention 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms MT4LC16M4G3, MT4LC16M4H9 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html PIN ASSIGNMENT (Top View) 32-Pin SOJ VCC DQ0 DQ1 NC NC NC NC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32-Pin TSOP VCC DQ0 DQ1 NC NC NC NC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vss DQ3 DQ2 NC NC NC CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 Vss OPTIONS Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) Timing 50ns access 60ns access Refresh Rates Standard Refresh Self Refresh (128ms period) MARKING H9 G3 DJ TG -5 -6 None S* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vss DQ3 DQ2 NC NC NC CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 Vss **NC on H9 version, A12 on G3 version 16 MEG x 4 EDO DRAM PART NUMBERS PART NUMBER MT4LC16M4H9DJ-x MT4LC16M4H9DJ-x S MT4LC16M4H9TG-x MT4LC16M4H9TG-x S MT4LC16M4G3DJ-x MT4LC1...