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MT4LC8M8C2 Dataheets PDF



Part Number MT4LC8M8C2
Manufacturers Micron Technology
Logo Micron Technology
Description DRAM
Datasheet MT4LC8M8C2 DatasheetMT4LC8M8C2 Datasheet (PDF)

8 MEG x 8 EDO DRAM DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x8 pinout, timing, functions, and packages • 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTLcompatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention MT4LC8M8P4, MT4LC8M8C2 For the.

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8 MEG x 8 EDO DRAM DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x8 pinout, timing, functions, and packages • 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTLcompatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention MT4LC8M8P4, MT4LC8M8C2 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html PIN ASSIGNMENT (Top View) 32-Pin SOJ VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32-Pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS OPTIONS • Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows • Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) • Timing 50ns access 60ns access • Refresh Rates Standard Refresh (64ms period) Self Refresh (128ms period) MARKING C2 P4 DJ TG -5 -6 None S* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC VSS DQ0 DQ7 DQ1 DQ6 DQ2 DQ5 DQ3 DQ4 NC Vss VCC CAS# WE# RAS# OE# NC/A12** A0 A1 A11 A2 A10 A3 A9 A4 A8 A5 A7 VCC A6 VSS **NC on C2 version and A12 on P4 version 8 MEG x 8 EDO DRAM PART NUMBERS PART NUMBER MT4LC8M8C2DJ-x MT4LC8M8C2DJ-x S MT4LC8M8C2TG-x MT4LC8M8C2TG-x S MT4LC8M8P4DJ-x MT4LC8M8P4DJ-x S MT4LC8M8P4TG-x MT4LC8M8P4TG-x S x = speed REFRESH ADDRESSING 4K 4K 4K 4K 8K 8K 8K 8K PACKAGE REFRESH SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP Standard Self Standard Self Standard Self Standard Self NOTE: 1. The 8 Meg x 8 EDO DRAM base number differentiates the offerings in one place— MT4LC8M8C2. The fifth field distinguishes the address offerings: C2 designates 4K addresses and P4 designates 8K addresses. 2. The “#” symbol indicates signal is active LOW. *Contact factory for availability Part Number Example: GENERAL DESCRIPTION The 8 Meg x 8 DRAM is a high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits and designed to operate from 3V to 3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 memory locations are arranged in 4,096 rows by 2,048 columns on the C2 version and 8,192 rows by 1,024 columns on the P4 version. During READ or WRITE cycles, each location is MT4LC8M8C2DJ-5 KEY TIMING PARAMETERS SPEED -5 -6 tRC tRAC tPC tAA tCAC tCAS 84ns 104ns 50ns 60ns 20ns 25ns 25ns 30ns 13ns 15ns 8ns 10ns 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM FUNCTIONAL BLOCK DIAGRAM MT4LC8M8P4 (13 row addresses) WE# CAS# DATA-IN BUFFER 8 DQ0DQ7 CONTROL LOGIC NO. 2 CLOCK GENERATOR DATA-OUT BUFFER 8 8 OE# 10 COLUMNADDRESS BUFFER(10) REFRESH CONTROLLER 10 COLUMN DECODER 1,024 SENSE AMPLIFIERS I/O GATING 1,024 x 8 8 A0A12 REFRESH COUNTER ROW SELECT 13 13 ROWADDRESS BUFFERS (13) COMPLEMENT SELECT ROW DECODER 13 8,192 8,192 x 8 8,192 x 1,024 x 8 MEMORY ARRAY RAS# NO. 1 CLOCK GENERATOR VDD VSS FUNCTIONAL BLOCK DIAGRAM MT4LC8M8C2 (12 row addresses) WE# CAS# DATA-IN BUFFER 8 DQ0DQ7 CONTROL LOGIC NO. 2 CLOCK GENERATOR DATA-OUT BUFFER 8 8 OE# 11 COLUMNADDRESS BUFFER(11) REFRESH CONTROLLER 11 COLUMN DECODER 2,048 SENSE AMPLIFIERS I/O GATING 2,048 x 8 8 A0A11 REFRESH COUNTER ROW SELECT 12 12 ROWADDRESS BUFFERS (12) COMPLEMENT SELECT ROW DECODER 12 4,096 4,096 x 8 4,096 x 2,048 x 8 MEMORY ARRAY RAS# NO. 1 CLOCK GENERATOR VDD VSS 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM GENERAL DESCRIPTION (continued) uniquely addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address is latched by CAS#. Both devices provide EDOPAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row. The 8 Meg x 8 DRAM must be refreshed periodically in order to retain stored data. EDO PAGE MODE DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If CAS# went HIGH and OE# was LOW (active), the output buffers would be disabled. The 8 Meg x 8 DRAM offers an accelerated page mode cycle by eliminating output disable from CAS# HIGH. This option is called EDO, and it allows CAS# precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms in the noted appendix). EDO operates like any DRAM READ or FAST-PAGEMODE READ, except data is held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH.


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