MT4LC8M8E1

8 MEG x 8 FPM DRAM DRAM FEATURES Single +3.3V ±0.3V power supply Industry-standard x8 pinout, timing, functions, and packages 13 row, 10 column addresses (E1) or 12 row, 11 column addresses (B6) High-performance CMOS silicon-gate process All inputs, outputs and clocks are LVTTLcompatible FAST PAGE MODE (FPM) access 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms Optional self refresh (S) for low-power data retention MT4LC8M8E1, MT4LC8M8B6 For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/dramds.html PIN ASSIGNMENT (Top View) 32-Pin SOJ VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32-Pin TSOP VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS OPTIONS Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) Timing 50ns access 60ns access Refresh Rates Standard Refresh (64ms period) Self Refresh (128ms period) MARKING B6 E1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ7 DQ6 DQ5 DQ4 Vss CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS **A12 on E1 version, NC on B6 version DJ TG 8 MEG x 8 FPM DRAM PART NUMBERS PART NUMBER REFRESH ADDRESSING 8K 8K 8K 8K 4K 4K 4K 4K PACKAGE REFRESH SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP ...