Document
Document Title
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Memory Revision History
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Preliminary HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Revision No.
History
Initial Draft. 1) Add Errata tCLS Specification Relaxed value 0 5 Case Specification Read(all) Except for tCLH tWP tALS tALH 10 15 tRC 50 50 60 25 45 0 5 10 15 tDS 20 25 tWC 50 70 tR 25us 27us
Draft Date
Nov. 19. 2004
Remark
Preliminary
tRP tREH tREA 20 20 25 20 20 30 30
0.1
Relaxed value ID Read ID Read 2) Add note.4(table14)
3) Add application note(Power on/off Sequence & Auto sleep mode) - Texts & figures are added. 4) Change AC parameters Case Before After x8, x16 x8 x16 tDH 10 10 15
1) Change AC parameters
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Jan. 20. 2005
Preliminary
case
x8, x16
2) Add tADL(=100ns) parameters 3) Add Muliti Die Concurrent Operations and Extended Read Status - Texts and table are added. 4) Edit Table.8 5) Change FBGA Package Dimension
Mar. 03. 2005 Preliminary
Rev 0.2 / Mar. 2005
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Preliminary HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities FAST BLOCK ERASE - Block erase time: 2ms (Typ.) STATUS REGISTER ELECTRONIC SIGNATURE - Manufacturer Code - Device Code SUPPLY VOLTAGE - 3.3V device: VCC = 2.7 to 3.6V : HY27UGXX2G2M CHIP ENABLE DON'T CARE OPTION - Simple interface with microcontroller AUTOMATIC PAGE 0 READ AT POWER-UP OPTION - Boot from NAND support - Automatic Memory Download SERIAL NUMBER OPTION HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions DATA INTEGRITY - 100,000 Program/Erase cycles - 10 years Data Retention PACKAGE - HY27(U/S)G(08/16)2G2M-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27(U/S)G(08/16)2G2M-T (Lead) - HY27(U/S)G(08/16)2G2M-TP (Lead Free) - HY27(U/S)G(08/16)1G2M-V(P) : 48-Pin WSOP1 (12 x 17 x 0.7 mm) - HY27(U/S)G(08/16)2G2M-V (Lead) - HY27(U/S)G(08/16)2G2M-VP (Lead Free) - HY27(U/S)G(08/16)1G2M-F(P) : 63-Ball FBGA (9.5 x 12 x 1.2 mm) - HY27(U/S)G(08/16)2G2M-F (Lead) - HY27(U/S)G(08/16)2G2M-FP (Lead Free)
- 1.8V device: VCC = 1.7 to 1.95V : HY27SGXX2G2M Memory Cell Array = (2K+ 64) Bytes x 64 Pages x 2,048 Blocks = (1K+32) Words x 64 pages x 2,048 Blocks PAGE SIZE - x8 device : (2K + 64 spare) Bytes : HY27(U/S)G082G2M - x16 device: (1K + 32 spare) Words : HY27(U/S)G162G2M
BLOCK SIZE - x8 device: (128K + 4K spare) Bytes - x16 device: (64K + 2K spare) Words PAGE READ / PROGRAM - Random access: 25us (max.) - Sequential access: 50ns (min.) - Page program time: 300us (typ.) COPY BACK PROGRAM MODE - Fast page copy without external buffering
CACHE PROGRAM MODE - Internal Cache Register to improve the program throughput
Rev 0.2 / Mar. 2005
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Preliminary HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash 1. SUMMARY DESCRIPTION
The HYNIX HY27(U/S)G(08/16)2G2M series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block. Data in the page mode can be read out at 50ns cycle time per word. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modifying can be locked using the WP# input pin or using the extended lock block feature described later. The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the RB# pins can be connected all together to provide a global status signal. Even the write-intensive systems can take advantage of the HY27(U/S)G(08/16)2G2M extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. Optionally the chip could be o.