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w power The superior performance of voltage controlled switch makes this device the preferred one in modern electronics applications.
The L6353 is a new monolithic integrated circuit designed to realise a versatile and smart interface between the signal circuitry and every kind of voltage controlled power switch, with a minimal design time and a reduction of parts count.
Device Description The L6353 is a smart silicon device which integrates all the circuitry for a versatile and rugged gate driver. The chip implements several features such as: an easy-to-link signal source by means of either an optocoupler or pulse transformer, a two-step turn-on procedure of the external power switch (dedicated to IGBT driving), a switch dropout voltage monitoring, the possibility to give a negative bias to the gate, the external programmability of safety thresholds and delays, the syncronisation and edge aligning and a powerful buffer of ±8A with split output. To introduce the device see fig.1 which shows the functional diagram: Figure 1. L6353 - Functional diagram
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AN556 APPLICATION NOTE THE L6353: A SMART GATE DRIVER
by: C. Adragna and G. Comandatore
2.5V 300mA SELECT
+
1.25V
-
INPUT
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INV-OUT ALARM
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+ -
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FILTER 200ns 3.75V
S a
DELAY
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+ -
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Supply UV Lockout References
REF
VPOS
OUT1 OUT1 CLAMPING CLAMP-PROG OUT2 LOGIC
3.15V
THERMAL SHUTDOWN
-
VSS 3.15V MON-DELAY
+ -
1.25V
+
3.75V VON-SENSE
+
ON-LEV-PROG
-
7.5V COM
AN556/0497
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AN556 APPLICATION NOTE
FUNCTIONAL DESCRIPTION Interfacing L6353 to the signal source A typical switching application requires a good noise immunity on the incoming signal to avoid the switch false triggering (turn-on/turn-off). Besides, electrical isolation and level shifting between the power and the signal parts can be needed. The L6353 is designed with the reference thresholds of control signal at 3.75V on rising edge and 1.25V on falling-edge (compatible with the CMOS output-levels), a fixed 200ns analog filter to eliminate glitches and some tricks to ease linking to the signal source. Figures 2, 3 and 4 sketch some practicable circuits and show the main signals. Fig.2 shows the direct feeding of control signal to the INPUT pin. The gate is driven in-phase by leaving the SELECT pin ats 2.5V (the phase is reversed if the pin is grounded). Figure 2. Direct interfacing and main waveforms.
RE F 1 00nF 2.5 V 3 00 m A S EL ECT + 10 0nF 1 .25 V Supp ly UV Lockou t Refere nces
OUT1 INPUT + FILTER 20 0ns Power & Co ntr ol V gate
Source
OUT2
COM
1 .25V
3.75 V
In applications requiring electrical isolation, the SELECT pin is designed especially for biasing a pulse transformer. Then, the quiescent level at INPUT pin is shifted to 2.5V and there is a differential threshold of +1.25V at switch-on and -1.25V at switch off. Figure 3. Pulse-transformer interfacing and main waveforms.
100nF
REF Supply UV Lockout References
2.5V 300µ A SELECT + 100nF
Source
1.25V 47Ω INPUT + -
-
FILTER 200ns
Power & Control
OUT1 Vgate
OUT2
COM
1.25V
3.75V
A cheap way to get the electrical isolation resorts to an optocoupler. In this case, the built-in 5V at VREF pin can be used to bias the optocoupler and, of course, the SELECT pin allows to manage the phase.
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AN556 APPLICATION NOTE
Figure 4. Optocoupler interfacing and main waveforms.
REF 100nF 2.5V 300 µA S ELE CT + 4.7k Ω 1.25V -
S upply UV Lockout References
470 Ω
INPUT + FILTER 200ns
Power & Control
O UT1 V gate
OUT2 COM
Source
1.25V
3.75V
Failure warning at the alarm output The L6353 sends an alarm signal in case of fault detection either in the chip or in the driven switch. The system monitors chip temperature, chip supply voltage and the switch voltage drop in on state. The fault signal, available at ALARM pin, is active low. The totem-pole output, with ±20mA current capability, is also useful (see fig.5) to get a signal either high or low on fault. Figure 5. ALARM circuitry and waveforms on power-on.
Active-low 4.7k Ω 4.7kΩ
Active-high
Positive Supply 100mF
VCC
ALARM
Supply UV Lockout References
Thermal Shutdown
ON-SENSE
Vdrop-switc h Iload
INPUT Power & Control
OUT1
OUT2 COM
Synchronising more switches Often, more switches must work synchronously. The synchronisation is always guaranteed by using the signal at OUTPUT instead of the one at INPUT, because of the L6353 safe processing. The INV-OUT pin is suitable for this function (see fig.6) because it sends a signal out of phase with the output, with ±20mA of current capability.
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AN556 APPLICATION NOTE
Figure 6. Master/Slave synchronisation.
RDEL
CDEL DELAY COM INV-OUT Load Supply
REF 100nF 5kΩ COM INPUT INPUT STAGE Supply UV Lockout References + 3.15V
OUT1 Power & Control Vgate2 OUT2 COM Iload CDEL DELAY INV-OUT LOAD OUT1 + Power & Control OUT2
3.15V
SELECT
RDEL
REF 100nF Supply UV Lockout Referenc.