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FW82439TX Dataheets PDF



Part Number FW82439TX
Manufacturers Intel
Logo Intel
Description Extended Temperature PCISET System Controller
Datasheet FW82439TX DatasheetFW82439TX Datasheet (PDF)

PRELIMINARY m o .c U 4 t e n e n h S a at n n .D n w w w Intel Extended Temperature 430TX PCISET: 82439TX System Controller (MTXC) Datasheet n Fully Synchronous, Minimum Latency 30/33-MHz PCI Bus Interface  Five PCI Bus Masters (including PIIX4)  10 DWord PCI-to-DRAM Read Prefetch Buffer  18 DWord PCI-DRAM Post Buffer  Multi-Transaction Timer to Support Multiple Short PCI Transactions Power Management Features  PCI CLKRUN# Support  Dynamic Stop Clock Support  Suspend to RAM (STR)  Susp.

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PRELIMINARY m o .c U 4 t e n e n h S a at n n .D n w w w Intel Extended Temperature 430TX PCISET: 82439TX System Controller (MTXC) Datasheet n Fully Synchronous, Minimum Latency 30/33-MHz PCI Bus Interface  Five PCI Bus Masters (including PIIX4)  10 DWord PCI-to-DRAM Read Prefetch Buffer  18 DWord PCI-DRAM Post Buffer  Multi-Transaction Timer to Support Multiple Short PCI Transactions Power Management Features  PCI CLKRUN# Support  Dynamic Stop Clock Support  Suspend to RAM (STR)  Suspend to Disk (STD)  Power On Suspend (POS)  Internal Clock Control  SDRAM and EDO Self Refresh During Suspend  ACPI Support  Compatible SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM)  SMM Writeback Cacheable in E_SMRAM Mode up to 1 MB  3.3/5V DRAM, 3.3/5V PCI 3.3/5V Tag and 3.3/2.5 SRAM Support Test Features  NAND Tree Support for all Pins Supports the Universal Serial Bus (USB) n The Intel 430TX PCIset (430TX) consists of the 82439TX System Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator (PIIX4). The 430TX supports both mobile and desktop architectures. The 430TX forms a Host-to-PCI bridge and provides the second level cache control and a full function 64-bit data path to main memory. The MTXC integrates the cache and main memory DRAM control functions and provides bus control to transfers between the CPU, cache, main memory, and the PCI Bus. The second level (L2) cache controller supports a writeback cache policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache memory can be implemented with pipelined burst SRAMs or DRAM cache SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line status bits. For the MTXC DRAM controller, six rows are supported for up to 256 Mbytes of main memory. The MTXC is highly integrated by including the Data Path into the same BGA chip. Using the snoop ahead feature, the MTXC allows PCI masters to achieve full PCI bandwidth. For increased system performance, the MTXC integrates posted write and read prefetch buffers. The 430TX integrates many Power Management features that enable the system to save power when the system resources become idle. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 430TX PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property of their respective owners. m o .c U 4 t e e h S a t a .D w w w n n n © INTEL CORPORATION 1999 February 1999 Supports Mobile and Desktop ® Supports the Pentium Processor Family Host Bus at 66 MHz and 60 MHz at 3.3V and 2.5V PCI 2.1 Compliant Integrated Data Path Integrated DRAM Controller  4 Mbytes to 256 MBytes main memory  64-Mbit DRAM/SDRAM Technology Support  FPM (Fast Page Mode), EDO and SDRAM DRAM Support  6 RAS Lines Available  Integrated Programmable Strength for DRAM Interface  CAS-Before-RAS Refresh, Extended Refresh and Self Refresh for EDO  CAS-Before-RAS and Self Refresh for SDRAM Integrated L2 Cache Controller  64-MB DRAM Cacheability  Direct Mapped Organization—Write Back Only  Supports 256K and 512K Pipelined Burst SRAM and DRAM Cache SRAM  Cache Hit Read/Write Cycle Timings at 3-1-1-1  Back-to-Back Read/Write Cycles at 3-1-1-1-1-1-1-1  64K x 32 SRAM also supported n 324-Pin MBGA 430TX PCIset Xcelerated Controller (MTXC) with integrated Data Paths m o .c U 4 t e e h S a at .D w w w Order Number: 273234-001 Extended Temperature 82439TX (MTXC) Datasheet H D [6 3 :0 ] A [3 1 :0 ] B E [7 :0 ]# ADS# D /C # M /IO # W /R # BRDY# EADS# H IT M # BO FF# AHO LD NA# K E N # /IN V CACHE# HLOC K# S M IA C T # CCS# TW E# CO E# GW E# CADS# CADV# T IO [7 :0 ] K R Q A K /C S 4_ 64# BW E# H ost In te rfa c e PCI In te rfa c e C LK R U N # A D [3 1 :0] C /B E [3:0]# FRAM E# TRDY# IR D Y # STOP# PLOCK# DEVSEL# PAR R E Q [3 :0 ]# G N T [3 :0 ]# PH LD A# PH LD # M D [6 3 :0 ] S R A S [A ,B ]# R A S [5 :0 ]# /C S [5 :0 ]# C A S [7 :0 ]# /D Q M [7 :0 ]# M A [1 1 :0 ] S C A S [A ,B ]# MW E# MW EB# C K E /M A A 0 , C K E B /M A A 1 DRAM In te rfa c e C ache In te rfa ce C lo c k s , R e s e t, T e s t, and Power M gnt H C L K IN P C L K IN RST.


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