MC56F8014

56F8014 Data Sheet Preliminary Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8014 Rev. 3 9/2005 freescale.com Document Revision History Version History Rev 0 Rev 1 Initial release Updates to Part 10, Specifications, Table 10-1, added maximum clamp current , per pin Table 10-11, clarified variation over temperature table and graph Table 10-15, added LIN slave timing Added alternate pins to Figure 11-1 and Table 11-1. Corrected bit selects in Timer Channel 3 Input (TC3_INP) bit 9 , Section 6.3.1.7, clarified Section 1.4.1, and simplified notes in Table 10-9, Description of Change Rev 2 Rev 3 Please see http://www.freescale.com for the most current Data Sheet revision. 56F8014 Technical Data, Rev. 3 2 Freescale Semiconductor Preliminary 56F8014 General Description Up to 32 MIPS at 32MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture 16KB Program Flash 4KB Unified Data/Program RAM One 5-channel PWM module Two 4-channel 12-bit ADCs One Serial Communication Interface (SCI) with LIN slave functionality One Serial Peripheral Interface (SPI) One 16-bit Quad Timer One Inter-Integrated Circuit (I2C) Port Computer Operating Properly (COP)/Watchdog On-Chip Relaxation Oscillator Integrated Power-On Reset and Low-Voltage Interrupt Module JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging Up to 26 GPIO lines 32-pin LQFP Package RESET 4 VCAP VDD VSS_IO 2 VDDA VSSA 5 PWM O...