AD9513

Data Sheet 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs AD9513 FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust Three 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 300 fs rms Time delays up to 11.6 ns Device configured with 4-level logic pins Space-saving, 32-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independent clock outputs that can be set to either LVDS or CMOS levels. These outputs operate to 800 MHz in LVDS mode and to 250 MHz in CMOS mode. Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment. CLK CLKB SYNCB FUNCTIONAL BLOCK DIAGRAM RSET VS GND /1. . . /32 AD9513 LVDS/CMOS OUT0 OUT0B /1. . . /32 LVDS/CMOS OUT1 OUT1B /1. . . /32 LVDS/CMOS OUT2 ∆t ...