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t e e h SPECIFICATION FOR LCD MODULE S a t a D .
Model No. TM128160EKFWG1
4U
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m o c
Prepared by: Checked by : Verified by : Approved by:
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Ver. 1.0
REVISION RECORD Date Ver. Ref. Page Revision No. Revision Items
1/25
Ver1.0
1. General Specifications:
1.1 Display type: COLOR STN 1 1.2 Display color* : Display color: 65K COLOR Background*2: Black (Red, Green, Blue dots are off state) 1.3 Polarizer mode: Transmissive/Negative 1.4 Viewing Angle: 6:00 1.5 Driving Method: 1/160 Duty 1/5 Bias 1.6 Backlight Type: LED (3 LAMPS) Backlight Color: WHITE 1.7 Controller: S6B33B0A03-B0CY 1.8 Data Transfer: 8/16 Bits Parallel or 3/4-PIN Serial Interface 1.9 Operating Temperature: -20~+70℃ Storage Temperature: -30~+80℃ 1.10 Power Supply Voltage: VDD=3.0V 1.11 LCD Operating Voltage: VLCD=16.8V 1.12 Outline Dimensions: Refer to outline drawing on next page 1.13 Dot Matrix: 128×3 (RGB)×160 Dots 1.14 Dot Size: 0.227(R+G+B)×0.215(mm2) 1.15 Dot Pitch: 0.237×0.225 (mm2) 1.16 Weight: TBD*3 *1 Color tone is slightly changed by temperature and driving voltage. *2 Color tone will be changed by backlight. *3 TBD: To Be Determined.
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Ver1.0
2. Outline Drawing
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Ver1.0
3. LCD Module Part Numbering System
TM 128160 E K F W G 1
MODIFICATION CODE DESIGNATOR IC PACKAGE G: COG TEMPRATURE RANGE W: WIDE TEMPERATURE RANGE BACKLIGHT TYPE F: TRANSMISSIVE, LED BACKLIGHT LCD TYPE K: COLOR STN MODE NEGATIVE MODULE SERIES MODULE TYPE DIGITS INDICATING: 128 (RGB) COLUMNS X 160 ROWS T: TIANMA M: MODULE
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Ver1.0
4. Circuit Block Diagram
×
......
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Ver1.0
5. Absolute Maximum Ratings
Ta=25℃ Item Power Supply Voltage LCD Driving Voltage Operating Temperature Range Storage Temperature Range Symbol VDD-VSS VLCD TOP Min. -0.3 -0.3 -20 Max. +4.6 V +20.0 +70 ℃ TST -30 +80 Unit Remark
No Condensation
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Ver1.0
6. Electrical Specifications and Instruction Code
6.1 Electrical characteristics Item Supply Voltage (Logic) Supply Voltage (LCD Drive) High Symbol VDD-Vss Min. +3.1 Vss=0V, Ta=25℃ Typ. +3.6 Max. +4.5 Unit V
VLCD VIH (VDD=3.0)
-
16.8
-
V
Input Signal Voltage
0.8VDD
-
VDD
V
Low
VIL
(VDD=3.0) IDD (VDD- VSS=3.0V)
0
-
0.2VDD
V
Supply current (Logic)
-
-
2.5
mA
Oscillator frequency range Supply Voltage (LED) Supply current (LED)
fosc
220
-
330
KHz
VLED
-
10.0
-
V
ILED
15.0
20.0
mA
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Ver1.0
6.2 Interface Signals 6.2.1 CN1(FPC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol PS MPU1 MPU0 CS RST RS WR(R/W) RD(E) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 Level H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L H/L
8/25 Ver1.0
Description
PS H H H H L L MPU1 L L H H L H MPU0 L H L H X X MPU inter-face select 8080-series 8bit interface 8080-series 16bit interface 6800-series 8bit interface 6800-series 16bit interface 3 pin SPI(Write only) 4 pin SPI(Write only)
Chip select: Low active Reset pin: Low active Index register / Data command select 6800-series 8080-series 6800-series 8080-series ReadWRBite control input pin Write enable clock input pin Read / Write control input pin Read enable clock input pin
Data bus bit 0-7. Only DB[7:6] are valid in serial interface mode (DB[5:0]: high impedance, DB[6]: serial clock, DB[7]: serial data).
Data bus bit 8-15. Connect DB[15:8] “low” only in 8-series parallel interface mode.
25 26
VDD VSS
3.0V 0V
Main power supply, 3VDC Ground
6.2.2 CN2(LED) Pin No. Symbol Level Description 1, 2 CATHODE 0V LED CATHODE 3, 4 ANODE 10.0V LED ANODE
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Ver1.0
6.3 Interface Timing Chart
Read / Write Characteristics (8080-series MPU)
D/I tAS80 /CS1 (CS2) tPW L80(R), /RD, /W R 0.9V DD 0.1V DD tDS80 DB0 to DB7 (W rite) tACC80 DB0 to DB7 (Read)
** tPWL80(W) and tPWL80(R) is specified in the overlapped period when CS1B is low (CS2 is high) and /W R(/RD) is low.
tAH80
tCY80 tPW L80(W )
tPW H80(R), tPW H80(W )
tDH80
tOD80
Parallel Interface (8080-series MPU) Timing Diagram
AC Characteristics (8080-series Parallel Mode) (VDD3 = 1.8 to 3.3V, Ta = -30 to +70°C) Min. Max. Unit (3.3V/1.8V) 3.3V 1.8V
0 0
150
50 30 50 30
5 8
CL = 100 pF
Item
Address setup time Address hold time
System cycle time
Pulse width low for write Pulse width High for write
Pulse width low for read Pulse width high for read
Signal
D/I
Symbol
tAS80 tAH80
tCY80
tPWLW tPWHW tPWLR tPWHR
tDS80 tDH80
tACC80 tOD80
Condition
0 0
360
100 75 100 75
10 14
tEWHR
60 / 120
ns
ns
ns ns
ns
ns
WRB (WRB) RDB (RDB)
DB0 to DB15
Data setup time Data hold time
Read access time Output disable time
NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read
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V1.0
Read / Write Characteristics (6800-series Microprocesso.