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ICS9147-03 Dataheets PDF



Part Number ICS9147-03
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Frequency Generator & Integrated Buffers
Datasheet ICS9147-03 DatasheetICS9147-03 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS9147-03 Frequency Generator & Integrated Buffers for 686 Series CPUs General Description The ICS9147-03 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro, AMD or Cyrix processors. Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table. The Six BUS clocks can be selected as either synchronous at 1/2 CPU speed or asynchronous at 32MHz selected by BSEL latched .

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Integrated Circuit Systems, Inc. ICS9147-03 Frequency Generator & Integrated Buffers for 686 Series CPUs General Description The ICS9147-03 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro, AMD or Cyrix processors. Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table. The Six BUS clocks can be selected as either synchronous at 1/2 CPU speed or asynchronous at 32MHz selected by BSEL latched input.The inputs provide for tristate and test mode conditions to aid in system level testing.These multiplying factors can be customized for specific applications. Glitch-free stop clock controls provided for SDRAM(5:8) and SDRAM (9:12) banks (STP2#, STP3#). High drive BUS and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffer supply pin VDDL allows for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPUL (1:2) and IOAPIC outputs. Features • Total of 15 CPU speed clocks: - Two copies of CPU clock with VDDL (2.5 to 3.3V) - Twelve (12) SDRAM (3.3v) plus one CPUH/AGP (3.3V) clocks Six copies of BUS clocks (synchronous with CPU clock/2 or asynchronous 32 MHz) 250ps output skew window for CPU andSDRAM clocks and 500ps window BUS clocks. CPU clocks to BUS clocks skew 1-4ns (CPU early) Two copies of Ref. clock @14.31818 MHz (One driven by VDDL as IOAPIC) One 48 MHz (3.3 V TTL) for USB support and single 24 MHz. Separate VDDL for CPUL (1:2) clock buffers and IOAPIC to allow 2.5V output (or Std. Vdd) 3.0V – 3.7V supply range w/2.5V compatible outputs 48-pin SSOP package • • • • • • • Block Diagram Pin Configuration 48-Pin SSOP Pentium is a trademark of Intel Corporation 9147-03 Rev A 04/25/01 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9147-03 Functionality with (14.31818 MHz input) Addre s s Se le ct FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPUL (1:2) CPUH SDRAM (1:12) (MHz) 60 66.8 50 55 75 68.5 Test/2** Tristate BUS (1:6) (M Hz) BSEL=1 30 33.4 25 27.5 37.5 34.3 Test/4** Tristate BSEL=0 32 32 32 32 32 32 Test/3** Tristate 24M (M Hz) (MHz) 24 24 24 24 24 24 Tristate 48M (M Hz) (MHz) 48 48 48 48 48 48 Tristate SDRAM Clock Enable DIMM DIMM DIMM STP2# STP3# BANK1 BANK2 BANK3 SDRAM SDRAM SDRAM (1:4) (5:8) (9:12) Stopped Stopped 0 0 ON Low Low Stopped 0 1 ON ON Low Stopped 1 0 ON ON Low 1 1 ON ON ON Test/4** Test/2** **Test: is the frequency applied to the X1 input. Can be crystal or tester generated clock overriding crystal at X1 pin. Pin Descriptions PI N N U M B E R 2 3, 9, 16, 22, 27, 33, 39, 45 4 5 41 8, 10, 11, 12, 14, 15 23, 24 R EF FS1 GN D X1 X2 VDDL BUS (1:5) BUS6 FS0 S TP # (2:3) 24M 47 1, 6, 13, 19, 30, 36, 48 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 40 42, 43 7, 25, 26 46 44 BS EL VDD3 S DRAM (1:12) C P UH/AGP CPUL (1:2) N /C 48M FS2 IO AP IC PI N N A M E TYPE O UT IN P WR IN O UT P WR O UT O UT IN IN O UT IN P WR O UT O UT O UT — O UT IN O UT D E S C R I PT I O N Reference clock output* Logic input frequency select Bit1*. Input latched at P oweron. Ground. C rystal input. N ominally 14.318 MHz. Has internal load cap C rystal output. Has internal load cap and feedack resistor to X1 2.5 or 3.3V buffer power for C P UL and IO AP IC output buffers. BUS clock outputs. see select table for frequency BUS clock output. S ee select table for frequency.* Logic input frequency select Bit0.*. Input latched at P oweron. Bank enable solutions for S DRAM clocks see table above, C locks are enabled in groups of 4. (S TP 2# stops DIMM bank2, S TP 3# stops DIMM bank 3 when low). 24MHz fixed clock.* Logic input* for selecting synchronous or asynchronous BUS frequencysee table above. Input latched at P oweron.* 3.3 volt core logic and buffer power S DRAM clocks at C P U speed. S ee select table for frequency. C P U clock operates at S DRAM VDD level (3.3V nom), for AGP etc. C P U clock output clocks .S ee select table for frequency. O perates at down to 2.5V controlled by VDDL pin. P ins not internally connected. 48 MHz fixed clock output*. Logic input frequency select Bit 2*. Input latched at P oweron. Reference clock (14.318MHz) powered by VDDL, operating 2.5 to 3.3V. * Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9147-03 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GN.


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