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ICS9147-01 Dataheets PDF



Part Number ICS9147-01
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Frequency Generator & Integrated Buffers
Datasheet ICS9147-01 DatasheetICS9147-01 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS9147-01 Frequency Generator & Integrated Buffers for PENTIUMTM General Description The ICS9147-01 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Two bidirectional I/O pins (FS1,FS2) are latched at power-on to the functionality table, with FS0 selectable in real-time to toggle between conditions. The inputs provide for tristate and test mode conditions to aid in system level testing. These multiplyin.

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Integrated Circuit Systems, Inc. ICS9147-01 Frequency Generator & Integrated Buffers for PENTIUMTM General Description The ICS9147-01 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Two bidirectional I/O pins (FS1,FS2) are latched at power-on to the functionality table, with FS0 selectable in real-time to toggle between conditions. The inputs provide for tristate and test mode conditions to aid in system level testing. These multiplying factors can be customized for specific applications. Glitch-free stop clockcontrols are provided for CPU clocks and BUS clocks. High drive BUS and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 50 ± 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffers supply pins VDD2 allow for 3.3V or reduced voltage swing (from 2.9 to 2.5V) for CPU (1:4) and IOAPIC outputs. Features • • • • • • • • • • • • • • Four copies of CPU clock Six SDRAM (3.3 V TTL), usable as AGP clocks Seven copies of BUS clock (synchronous with CPU clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU) CPU clocks to BUS clocks skew 1-4ns (CPU early) One IOAPIC clock @14.31818 MHz Two copies of Ref. clock @14.31818 MHz One each 48/ 24 MHz (3.3 V TTL) This device is configured into the Mobile mode for power management of Intel 430 TX Ref. 14.31818 MHz Xtal oscillator input Separate 66/60 MHz select pin (LSB of select pins) Separate VDD2 for four CPU and single IOAPIC output buffers to allow 2.5V output (or Std. Vdd) Power Management Control Input pins 3.0V – 3.7V supply range w/2.5V compatible outputs 48-pin SSOP package Block Diagram Pin Configuration 48-Pin SSOP Pentium is a trademark of Intel Corporation 9147-01Rev B 04/25/01 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9147-01 Pin Descriptions PI N N U M B E R 1 2 PI N N A M E R EF 2 FS2 R EF 1 FS1 TYPE O UT IN O UT IN PWR IN O UT PWR O UT IN PWR O UT IN IN O UT PWR O UT IN O UT — D E S C R I PT I O N Reference clock output* Logic input frequency select Bit 2* Reference clock output* Logic input frequency select Bit1* Ground. Crystal input. N ominally 14.318 MHz. Has internal load cap. External crystal load of 30pF to GN D recommended for VDD power on faster than 2.0ms. Crystal output. Has internal load cap and feedback resistor to X1. External crystal load of 10pF to GN D recommended for VDD power on faster than 2.0ms. 3.3V I/O power supply, BUS and S DRAM buffer supply. BUS clock outputs. see select table for frequency S elect pin for enabling 66.6 MHz or 60 MHz, or other selections in frequency select table. C ore power supply, and fixed clock power. 48, 24MHz clock outputs Input pin to synchronously stop all BUS (1:6) clocks when pin is low. Input pin to synchronously stop all C PU and S DRAM clocks when pin is low. S DRAM clocks at C PU speed. S ee select table for frequency. Powered by VDD3. 2.5V Power S upply for C PU and IO APIC buffers, can be tied to VDD3 for 3.3V operation C PU clock output clocks .S ee select table for frequency Power down logic control input. When low, powers off both PLL and all outputs forced to logic low. IO APIC clock output (Freq=14.318 with nominal crystal) Powered by VDD2 supply Pins not internally connected. 3, 10, 17, 24, 31, GN D 37, 43 4 5 X1 X2 7, 15, 28, 34 VDD3 8,9,11,12,13,14,16 BUS F, BUS (1:6) 18 2 1, 2 5 , 4 8 22, 23 26 27 FSO VDD 48, 24MHz BUS S TO P# C PUS TO P# 36, 35, 33, 32, 30, S DRAM (1:6) 29 40, 46 41, 42, 39,38 44 45 6 , 19 , 2 0 , 4 7 VDD2 CPU (1:4) P D# IO AP IC N /C * Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9147-01 Functionality PD# 1 1 1 1 1 1 1 1 0 1 1 CPUSTOP# 1 1 1 1 1 1 1 1 1 0 1 BUSFS2* FS1* STOP# (at REF2) (at REF1) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 X X X FS0 (pin 18) 0 1 0 1 0 1 0 1 X X X CPU (1:4), BUS (1:6) SD R M BUSF (1:6) (M Hz) (M Hz) 60 30 66.6 33.3 50 25 55 27.5 75 30a 83.3 33.3a REF/2 REF/4 Tristate Tristate LOW LOW PLL off LOW running running LOW 48M Hz 24 M Hz (M Hz) (M Hz) 48 48 48 48 48 48 REF/2 Tristate LOW PLL off running running 24 24 24 24 24 24 REF/4 Tristate LOW running running REF (1:2), IOAPIC (M Hz) 14.318 14.318 14.318 14.318 14.318 14.318 REF Tristate LOW Osc Off running running Note a: These frequency selections are at CPU/2.5 (internal VCO/5), not synchronous CPU/2 3 ICS9147-01 CPUSTOP# Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPUSTOP# is synchronize.


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