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ICS9148-111 Dataheets PDF



Part Number ICS9148-111
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Frequency Generator & Integrated Buffers
Datasheet ICS9148-111 DatasheetICS9148-111 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS9148-111 Frequency Generator & Integrated Buffers for PENTIUM/ProTM Recommended Application: ALI (Aladdin V™ ) mobile. Output Features: • 3 - CPUs @ 2.5V/3.3V, up to 100MHz. • 3 - AGPCLK @ 3.3V • 13 - SDRAM @ 3.3V, up to 100MHz. • 6 - PCI @ 3.3V, including one free running. • 1 - 48MHz, @ 3.3V fixed. • 1 - REF @ 3.3V, 14.318MHz. Features: • Up to 100MHz frequency support • Support power management: CPU, PCI, AGP stop and, Power down Mode from I2C programming.

  ICS9148-111   ICS9148-111



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Integrated Circuit Systems, Inc. ICS9148-111 Frequency Generator & Integrated Buffers for PENTIUM/ProTM Recommended Application: ALI (Aladdin V™ ) mobile. Output Features: • 3 - CPUs @ 2.5V/3.3V, up to 100MHz. • 3 - AGPCLK @ 3.3V • 13 - SDRAM @ 3.3V, up to 100MHz. • 6 - PCI @ 3.3V, including one free running. • 1 - 48MHz, @ 3.3V fixed. • 1 - REF @ 3.3V, 14.318MHz. Features: • Up to 100MHz frequency support • Support power management: CPU, PCI, AGP stop and, Power down Mode from I2C programming. • Spread spectrum for EMI control (0 to -0.6%, ± 0.25%). • Uses external 14.318MHz crystal • FS pins for frequency select Key Specifications: • CPU – CPU: <250ps • SDRAM - SDRAM: <250ps • AGP-AGP: <250ps • PCI – PCI: <500ps • CPU-SDRAM <500ps • CPU(early)-PCI: 1-4ns, Center 2-6ns • CPU-AGP <500ps Pin Configuration 48-Pin 300mil SSOP * Internal Pull-up Resistor of 240K to 3.3V on indicated inputs Block Diagram Functionality CPU, PCI AGP FS2 FS1 FS0 SDRAM (MHz) (MHz) (MHz) 1 1 1 100 33.33 66.67 1 1 0 95.25 31.75 63.50 1 0 1 83.3 33.30 66.60 1 0 0 75 30.00 60.00 0 1 1 91.5 30.50 61.00 0 1 0 96.22 32.07 64.15 0 0 1 66.8 33.40 66.80 0 0 0 60 30.00 60.00 REF, IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 9148-111 Rev A 10/19/99 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-111 Pin Configuration PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6 7 FS11, 2 8 10, 11, 12, 13 14 15 17 PCICLK0 FS21, 2 PCICLK(1:4) VDD5 BUFFERIN CPU_STOP#1 SDRAM 11 18 28, 29, 31, 32, 34, 35,37,38 20 PCI_STOP#1 SDRAM 10 SDRAM (0:9) AGP_STOP# SDRAM9 21 19,30,36 23 24 25 MODE1, 2 48MHz 26 41, 43, 44 40 42 46, 47 48 FS01, 2 CPUCLK(0:3) SDRAM12 VDDL AGP (1:2) VDD4 IN OUT IN OUT OUT PWR OUT PWR PD# SDRAM8 VDD3 SDATA SCLK AGP0 IN OUT IN OUT PWR IN IN OUT IN OUT OUT IN OUT IN OUT PWR IN IN OUT P I N NA M E VDD1 REF0 C P U 3 . 3 # _ 2 . 5 1,2 GND X1 X2 VDD2 PCICLK_F TYPE PWR OUT IN PWR IN OUT PWR OUT DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 Mhz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t 2 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Supply for fixed PLL, 48MHz, AGP0 Input pin for SDRAM buffers. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP(1:2) clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Supply for SDRAM (0:11), CPU Core, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input Advanced Graphic Port output, powered by VDD4. Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Feedback SDRAM clock output. Supply for CPU (0:3), either 2.5V or 3.3V nominal Advanced Graphic Port outputs, powered by VDD4. Supply for AGP (0:2) Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. Third party brands and names are the property of their respective owners. 2 ICS9148-111 General Description The ICS9148-111 is a single chip clock solution for Desktop/ ™ Notebook designs using the ALI (Aladdin V ) mobile style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-111 employs a proprieta.


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