ADSP2195 Microcomputer Datasheet

ADSP2195 Datasheet, PDF, Equivalent


Part Number

ADSP2195

Description

DSP Microcomputer

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADSP2195 Datasheet


ADSP2195
35(/,0,1$5< 7(&+1,&$/ '$7$
aPrelitamSinheaeryt4TUe.ccohmnical Data DSP MAicDrSoPc-o2m1p9u5terADSP-219x DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
a160 MIPS Sustained Performance
.DADSP-218x Family Code Compatible with the Same
wEasy -to-Use Algebraic Syntax
Single-Cycle Instruction Execution
w Up to 16M words of Addressable Memory Space with
w 24 Bits of Addressing Width
mDual Purpose Program Memory for Both Instruction and
Data Storage
oFully Transparent Instruction Cache Allows Dual
Operand Fetches in Every Instruction Cycle
.cUnified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code
Execution at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C
Code Efficiency
eet4U$'63[
h'6 3 &2 5 (
FUNCTIONAL BLOCK DIAGRAM
,17(55837 &21752//(5
7,0 ( 5 6 ) /$ * 6
&$&+(
× % ,7
,17(51$/ 0 (02 5<
7:2 ,1'(3( 1'(17 %/2&.6
$'' 5(6 6
$'' 5(6 6
'$7$
'$7$
S' $ * 
× × 
'$*
× × 
352*5$0
6( 4 8 ( 1& ( 5
ta30 $''5( 66 %8 6

a' 0 $' ' 5 ( 6 6 % 8 6


'0$
$'' 5(6 6

'0$
'$7$
.D%86
w&2 11 (&7
3;
30 '$7$ %86
'0 '$7$ %86
w' $ 7 $
5( * ,67 (5
m) , / (
w o,1387
5( * ,6 7( 56
et4U.c0 8 / 7
5(68/7
5( * ,6 7( 56
× %,7
%$55(/
6 + ,) 7 (5


$/8
,2 5(*,67(56
0(025< 0$33('
&21752/
67$786
%8))(56
'0$
&21752//(5
ataSheREV. PrA
-7$*
7(67
(0 8/ $ 7,2 1

(;7(51$/
3257
$''5 %86
08;

(;7(51$/ 0(025<
,17( 5 )$& (
'$7$ %86
08;

,2 352&(6625
+267 3257
6(5,$/ 32576

63, 32576

8$57 3257





w.DThis information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
wassumes no obligation regarding future manufacturing unless otherwise
wagreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2001

ADSP2195
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2195
For current information contact Analog Devices at 800/262-5643
September 2001
ADSP-2195 DSP FEATURES
32K Words of On-Chip RAM, Configured as 16K Words
On-Chip 24-bit RAM and 16K Words On-Chip
16-bit RAM
16K Words of On-Chip 24-bit ROM
Architecture Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, Ports, and Peripherals
Flexible Power Management with Selectable
Power-Down and Idle Modes
Programmable PLL Supports 1؋ to 32؋ Frequency
Multiplication, Enabling Full-Speed Operation from
Low-Speed Input Clocks
2.5 V Internal Operation Supports 3.3 V Compliant I/O
Three Full-Duplex Multichannel Serial Ports, Each
Supporting H.100 Standard with A-Law and -Law
Companding in Hardware
Two SPI-Compatible Ports with DMA Capability
One UART Port with DMA Capability
16 General-Purpose I/O Pins (Eight Dedicated/Eight
Programmable from the External Memory Interface)
with Integrated Interrupt Support
Three Programmable 32-Bit Interval Timers with
Pulsewidth Counter, PWM Generation, and Externally
Clocked Timer Capabilities
Up to 11 DMA Channels can be Active at any Given Time
Host Port With DMA Capability for Efficient, Glueless Host
Interface (16-Bit Transfers)
External Memory Interface Features Include:
Direct Access from the DSP to External Memory for
Data and Instructions.
Support for DMA Block Transfers to/from
External Memory.
Separate Peripheral Memory Space with Parallel
Support for 224K External 16-Bit Registers.
Four General-Purpose Memory Select Signals that
Provide Access to Separate Banks of External
Memory. Bank Boundaries and Size Are User-
Programmable.
Programmable Waitstate Logic with ACK Signal and
Separate Read and Write Wait Counts. Wait Mode
Completion Supports All Combinations of ACK
and/or Wait Count.
I/O Clock Rate Can Be Set to the Peripheral Clock Rate
Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow
Memory Devices.
Address Translation and Data Word Packing is Provided
to Support an 8- or 16-Bit External Data Bus.
Programmable Read and Write Strobe Polarity.
Separate Configuration Registers for the Four
General-Purpose, Peripheral, and Boot
Memory Spaces.
Bus Request and Grant Signals Support the Use of the
External Bus by an External Device.
Boot Methods Include Booting Through External Memory
Interface, SPI Ports, UART Port, or Host Interface
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
144-Lead LQFP Package (20 ؋ 20 ؋ 1.4 mm) and 144-Lead
Mini-BGA Package (10 ؋ 10 ؋ 1.25 mm)
2
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrA
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.


Features 35(/,0,1$5< 7(&+1,&$/ '$7$ a U 4 t w w m o .c e e Preliminary Technical Data h S a at .D w ADSP-219x DSP CORE FEATU RES 6.25 ns Instruction Cycle Time (Int ernal), for up to 160 MIPS Sustained Pe rformance ADSP-218x Family Code Compati ble with the Same Easy -to-Use Algebrai c Syntax Single-Cycle Instruction Execu tion Up to 16M words of Addressable Mem ory Space with 24 Bits of Addressing Wi dth Dual Purpose Program Memory for Bot h Instruction and Data Storage Fully Tr ansparent Instruction Cache Allows Dual Operand Fetches in Every Instruction C ycle Unified Memory Space Permits Flexi ble Address Generation, Using Two Indep endent DAG Units DSP Microcomputer ADS P-2195 Independent ALU, Multiplier/Accu mulator, and Barrel Shifter Computation al Units with Dual 40-bit Accumulators Single-Cycle Context Switch between Two Sets of Computational and DAG Register s Parallel Execution of Computation and Memory Instructions Pipelined Architec ture Supports Efficient Code Execution at Speeds up to 160 MIPS.
Keywords ADSP2195, datasheet, pdf, Analog Devices, DSP, Microcomputer, DSP2195, SP2195, P2195, ADSP219, ADSP21, ADSP2, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)