ADSP-2192M Microcomputer Datasheet

ADSP-2192M Datasheet, PDF, Equivalent


Part Number

ADSP-2192M

Description

DSP Microcomputer

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADSP-2192M Datasheet


ADSP-2192M
ataSheet4U.com DSP MADicSrPo-c2o1m9p2uMterADSP-2192M DUAL CORE DSP FEATURES
320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package
awith PCI, USB, Sub-ISA, and CardBus Interfaces
.D3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface
wwith Bus Mastering over Four DMA Channels with
Scatter-Gather Support
w Integrated USB 1.1 Compliant Interface
w Sub-ISA Interface
mAC’97 Revision 2.1 Compliant Interface for External
Audio, Modem, and Handset Codecs with DMA
oCapability
Dual ADSP-219x Core Processors (P0 and P1) on Each
.cADSP-2192M DSP Chip
132K Words of Memory Includes 4K ؋ 16-Bit Shared
Data Memory
80K Words of On-Chip RAM on P0, Configured as
64K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
48K Words of On-Chip RAM on P1, Configured as
32K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
4K Words of Additional On-Chip RAM Shared by Both
Cores, Configured as 4K Words On-Chip 16-Bit RAM
Flexible Power Management with Selectable Power-
Down and Idle Modes
Programmable PLL Supports Frequency Multiplication,
Enabling Full Speed Operation from Low Speed
Input Clocks
2.5 V Internal Operation Supports 3.3 V/5.0 V
Compliant I/O
heet4UADSP-219x
SDSP CORE
FUNCTIONAL BLOCK DIAGRAM
P0
MEMORY
16K؋24 PM
64K؋16 DM
BOOT ROM
ADDR DATA
SHARED
MEMORY
4K؋16 DM
ADDR DATA
P1
MEMORY
16K؋24 PM
32K؋16 DM
BOOT ROM
ADDR DATA
ADSP-219x
DSP CORE
ta(SEE FIGURE 1
ON PAGE 3)
.DaCORE
INTERFACE
PROCESSOR P0
ADDR DATA
P0 DMA
w CONTROLLER
w FIFOS
ADDR DATA
SHARED DSP
I/O MAPPED
REGISTERS
(SEE FIGURE 1
ON PAGE 3)
CORE
INTERFACE
ADDR DATA
PROCESSOR P1
P1 DMA
CONTROLLER
FIFOS
w t4U.comGP I/O PINS
(AND
eOPTIONAL
SERIAL
eEEPROM)
SERIAL PORT
AC'97
COMPLIANT
HOST PORT
PCI 2.2
OR
USB 1.1
JTAG
EMULATION
PORT
ataShREV. 0
.DInformation furnished by Analog Devices is believed to be accurate and
wreliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
wmay result from its use. No license is granted by implication or otherwise
wunder any patent or patent rights of Analog Devices. Trademarks and
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
registered trademarks are the property of their respective companies.
Fax:781/326-8703
© 2002 Analog Devices, Inc. All rights reserved.

ADSP-2192M
ADSP-2192M
ADSP-2192M DUAL CORE DSP FEATURES (continued)
Eight Dedicated General-Purpose I/O Pins with Integrated
Interrupt Support
Each DSP Core Has a Programmable 32-Bit Interval Timer
Five DMA Channels Available on Each Core
Boot Methods Include Booting Through PCI Port, USB
Port, or Serial EEPROM
JTAG Test Access Port Supports On-Chip Emulation and
System Debugging
144-Lead LQFP Package
DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
160 MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same Easy
to Use Algebraic Syntax
Single-Cycle Instruction Execution
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual Operand
Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-Bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code Execution
at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C/C++ Code
Efficiency
Architecture Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, Ports, and Peripherals
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3
DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Register Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CardBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Using the PCI Interface . . . . . . . . . . . . . . . . . . . . . . . 7
Using the USB Interface . . . . . . . . . . . . . . . . . . . . . 13
General USB Device Definitions . . . . . . . . . . . . . . . 17
Sub-ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PCI Interface to DSP Memory . . . . . . . . . . . . . . . . 22
USB Interface to DSP Memory . . . . . . . . . . . . . . . . 22
AC’97 Codec Interface to DSP Memory . . . . . . . . . 22
Data FIFO Architecture . . . . . . . . . . . . . . . . . . . . . 22
System Reset Description . . . . . . . . . . . . . . . . . . . . 23
Power Management Description . . . . . . . . . . . . . . . 24
Power Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 V Regulator Options . . . . . . . . . . . . . . . . . . . . . 24
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Instruction Set Description . . . . . . . . . . . . . . . . . . . 26
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 26
Additional Information . . . . . . . . . . . . . . . . . . . . . . 28
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 28
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 31
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 31
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 31
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 34
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Environmental Conditions . . . . . . . . . . . . . . . . . . . 35
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . 36
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 38
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 38
–2– REV. 0


Features m o .c U 4 t e e h S a at .D w w w a D SP Microcomputer ADSP-2192M 80K Words o f On-Chip RAM on P0, Configured as 64K Words On-Chip 16-Bit RAM for Data Memor y and 16K Words On-Chip 24-Bit RAM for Program Memory 48K Words of On-Chip RAM on P1, Configured as 32K Words On-Chip 16-Bit RAM for Data Memory and 16K Wor ds On-Chip 24-Bit RAM for Program Memor y 4K Words of Additional On-Chip RAM Sh ared by Both Cores, Configured as 4K Wo rds On-Chip 16-Bit RAM Flexible Power M anagement with Selectable PowerDown and Idle Modes Programmable PLL Supports F requency Multiplication, Enabling Full Speed Operation from Low Speed Input Cl ocks 2.5 V Internal Operation Supports 3.3 V/5.0 V Compliant I/O ADSP-2192M D UAL CORE DSP FEATURES 320 MIPS ADSP-219 x DSP in a 144-Lead LQFP Package with P CI, USB, Sub-ISA, and CardBus Interface s 3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/ 32-bit Interface with Bus Mastering ove r Four DMA Channels with Scatter-Gather Support Integrated USB 1.1 Compliant Interface Sub-ISA Interfa.
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