Audio Application. CXD2559 Datasheet

CXD2559 Application. Datasheet pdf. Equivalent

CXD2559 Datasheet
Recommendation CXD2559 Datasheet
Part CXD2559
Description 1-Bit D/A Converter For Audio Application
Feature CXD2559; ® HI2559, CXD2559 D NDE E M M FO R DES NEW S IG N October 1997 1-Bit D/A Converter For Audio Appl.
Manufacture Intersil Corporation
Datasheet
Download CXD2559 Datasheet




Intersil Corporation CXD2559
® HI2559, CXD2559
October 1997
Features
NOT
RECOMMENDED
FOR
NEW
DESIGNS
1-Bit D/A Converter
Description
For
Audio
Application
• Two-Channel D/A Converter and Oversampling Digital
Filter Into a Single Chip
• Distortion . . . . . . . . . . . . . . . . . . . . . . . . 0.012% or Less
• S/N Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . .96dB or More
• Master Clock . . . . . . . . . . . . . . . . . . . . . 384FS or 256FS
The HI2559, CXD2559 is a 1-bit stereo D/A converter featur-
ing a 2nd-order system noise shaper. This good cost per-
formance LSI has functions such as digital attenuator and
digital de-emphasis and others.
Ordering Information
Applications
• CD Player and CD-ROM Player, etc.
Functions
• Data Can Be Input at Rate of 1 x FS with a Built-In Digital
Filter
• The 24-/32-Slot Serial Data Interface Enables
Independent Selection of Data Frontward Trunca-
tion/Rearward Truncation and MSB First/LSB First
• Two Channels Can Be Attenuated Independently in 255
Steps
• The Output From Two Channels (L/R/L + R/Mute) Can
Be Selected Independently
• Digital Emphasis
PART
NUMBER
HI2559JCQ
CXD2559Q
TEMP.
RANGE (oC)
-20 to 75
-20 to 75
PACKAGE
32 Ld MPQF
32 Ld MPQF
PKG. NO.
Q32.7x7-S
Q32.7x7-S
Pinout
HI2559, CXD2559
(MQFP)
TOP VIEW
AVDD0
AOUT2-
AVSS0
DVDD0
TEST
CLR
MASL
DVSS0
1
3231
30
29
28
27
26
25
24
2 23
3 22
4 21
5 20
6 19
7 18
89
10
11
12
13
14
15
17
16
AVDD1
AOUT1-
AVSS1
DVSS1
XCLK
DASL0
DASL1
DVDD1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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File Number 4120.1



Intersil Corporation CXD2559
Block Diagram
XTLI
HI2559, CXD2559
XTLO
XCLK
LRCK
BCK
SIN
MASL
MLSL
ATT
SHIFT
LATCH
SP
HOST
COMPUTER
I/F
CLOCK GENERATOR
TIMING CIRCUIT
DIGITAL
FILTER
(OVER SAMPLING)
DAC1
DAC2
AOUT1 (+)
AOUT1 (-)
AOUT2 (+)
AOUT2 (-)
ROM
ATT1
ATT2
RAM
Pin Descriptions
PIN NO.
1
2
3
4
5
6
7
SYMBOL
AVDD0
AOUT2(–)
ADVSS0
DVDD0
TEST
CLR
MASL
8 DVSS0
9 LRCK
10 BCK
11 SIN
12 MLSL
I/O DESCRIPTION
- Analog power supply for Channel 2 output.
O Analog reversed phase output for Channel 2.
- Analog GND for Channel 2 output.
- Digital power supply.
I IC measurement. Fixed to Low.
I System clear input. Cleared when low. Equipped with a pull-up resistor.
I Selects whether 16-bit serial data is placed in the first 16-bit or the second 16-bit slot of the
serial IN 32-bit slots. Frontward truncation when High; rearward truncation when low.
Equipped with a pulldown resistor.
- Digital GND.
I Serial IN sampling frequency clock. Transfers Channel-1 data when High; Channel-2 data
when low.
I Serial bit transfer clock 48 FS or 64 FS in serial IN. The serial input data is retrieved at the
rising edge.
I Two channels per sampling serial data input. Data format is represented by 2’s comple-
ments, and consists of 24-bit or 32-bit slots.
I Selects whether 16-bit serial data SIN (Pin 15) of serial IN at LSB first or MSB first. MSB-
first when High; LSB-first when Low. Equipped with a pull-up resistor.
4-2



Intersil Corporation CXD2559
Pin Descriptions (Continued)
PIN NO.
13
SYMBOL
ATT
I/O
I
14
SHIFT
I
15 LATCH I
16 WO I
17 DVDD1 -
18 DASL1 I
19 DASL0 I
20
XCLK
O
21 DVSS1 -
22 AVSS1 -
23
AOUT1 (-)
O
24 AVDD1 I
25
AOUT1 (+)
O
26 AVSS2 -
27 XVDD -
28
XTLO
O
29 XTLI I
30 XVSS -
31 AVSS3 -
32
AOUT2 (+)
O
HI2559, CXD2559
DESCRIPTION
Data input of the microcomputer interface. Attenuation data, output selection setting value,
and de-emphasis on/off data re-input in serial mode.
Shift clock input of the microcomputer interface.
Latch input of the microcomputer interface. Latched at the rising edge.
Synchronization window control. Window open when Low (forced synchronization).
Digital power supply.
IC measurement. Fixed to Low.
IC measurement. Fixed High.
Inversion output of the clock input from XTLI (Pin 1).
Digital GND.
Analog GND for Channel 1 output.
Analog reversed phase output for Channel 1.
Analog power supply for Channel 1 output.
Analog positive phase output for Channel 1.
Analog GND for Channel 1 output.
Digital power supply for the master clock.
Crystal oscillator output. Connects the master clock 256 FS or 384 FS crystal oscillator,
which is identified automatically.
Crystal oscillator input. Connects the master clock 256 FS or 384 FS crystal oscillator,
which is identified automatically. External clock pulse is input at this pin.
Digital GND for master clock
Analog GND for Channel 2 output.
Analog positive phase output for Channel 2.
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