25FV101T LE25FV101T Datasheet

25FV101T Datasheet, PDF, Equivalent


Part Number

25FV101T

Description

LE25FV101T

Manufacture

Sanyo

Total Page 10 Pages
Datasheet
Download 25FV101T Datasheet


25FV101T
omPreliminary Specifications
CMOS LSI
LE25FV101T
t4U.c1M (128k words × 8bits) Serial Flash EEPROM
taSheeFeatures
CMOS Flash EEPROM Technology
aSingle 3.3-Volt Read and Write Operations
.DSector Erase Capability: 256 Bytes per sector
wOperating Frequency: 10MHz
wLow Power Consumption
w Active Current (Read): 25 mA (Max.)
High Read/Write Reliability
Sector-write Endurance Cycles: 104
10 Years Data Retention
Self-timed Erase and Programming
Byte Programming: 35 µs (Max.)
End of Write Detection: Status Register Read
Standby Current: 20 µA (Max.)
Serial Peripheral Interface (S.P.I.) mode 0.
Hardware Data Protection
Packages Available: MSOP8(225mil)
.comProduct Description
Device Operation
The LE25FV101T is a 128K x 8 CMOS sector
Uerase, byte programmable serial Flash EEPROM.
t4The LE25FV101T is manufactured using SANYO's
proprietary, high performance CMOS Flash
eEEPROM technology. Breakthroughs in EEPROM
cell design and process architecture attain better
ereliability and manufacturability compared with
conventional approaches. The LE25FV101T erases
hand programs with a 3.3-volt only power supply.
SLE25FV101T conforms to Serial Peripheral Interface
(S.P.I.).
taFeaturing high performance programming, the
aLE25FV101T typically byte programs in 35 µs. The
LE25FV101T typically sector (256 bytes) erases in
.D4ms. Both program and erase times can be
optimized using interface feature such as Status
Register to indicate the completion of the write cycle.
wTo protect against an inadvertent write, the
LE25FV101T has on chip hardware data protection
wscheme. Designed, manufactured, and tested for a
wide spectrum of applications, the LE25FV101T is
woffered with a guaranteed sector write endurance of
Commands are used to initiate the memory
operation functions of the device. Commands are
written to the command register through serial input
(SI). The addresses and data of Commands are
latched to be used to operate functions such as
Read, Sector_Erase, Byte_Program and so on.
Fig.3 and Fig.4 contain the timing waveforms of
serial input and output. By setting CS to LOW, the
device is selected. And commands, addresses, and
dummy bits can be let in serially through SI port.
When the device is in Read or Status Register Read
mode, SO pin is in Low-impedance state. And the
requested data can be read out from MSB (most
significant bit) synchronously with the falling edge of
SCK.
WP 1
Vcc 2
8 RESET
7 Vss
104 cycles. Data retention is rated greater than 10
myears.
.coThe LE25FV101T is best suited for applications
Uthat require re-programmable nonvolatile mass
t4storage of program or data memory.
CS
SCK
3
4
6 SO
5 SI
Figure1: Pin Assignment for 8-pin MSOP
ataShee*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This preliminary specification is subject to change without notice.
.DSANYO Electric Co., Ltd. Semiconductor Company
w1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
wwRevision c-November 1,1999-KI/ki-1/9

25FV101T
Preliminary Specifications
LE25FV101T
3.3V-only 1M-Bit Serial Flash EEPROM
ADDRESS
BUFFERS
&
LATCHES
X-
DECODER
1,048,576 Bit
Flash EEPROM
Cell Array
CONTROL
LOGIC
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
SERIAL INTERFACE
CS SCK SI
SO WP RESET
Figure2: Functional Block Diagram of LE25FV101T
Table1: Pin Description
Symbol Pin Description
SCK Serial Clock
SI Serial Input
SO Serial Output
CS Chip Select
WP Write Protect
Vcc
Vss
RESET
Power Supply
Ground
Reset
Functions
To control the timing of serial data input and output.
To latch input data and addresses synchronously at the rising edge of SCK, and read
out output data synchronously at this falling edge.
To input data or addresses serially from MSB to LSB (Least Significant Bit).
To output data serially from MSB to LSB.
To activate the device when this pin is LOW.
To deselect and put the device to standby mode when High.
To prevent inadvertent write when this pin is LOW.
As WP is connected internally to the Vcc, leave this pin open when this function is
not necessary.
To provide 3.0V to 3.6V supply.
To prevent inadvertent writes by setting this pin to LOW during system power-up.
As RESET is connected to Vcc internally, leave this pin open when this function is
not necessary.
Table2: Commands Summary
Command
1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle
OPcode
Address
Address
Address Data / OPcode Dummy
Read
FFH
A23-A16
A15-A8
A7-A0
X
X
Sector Erase
20H
A23-A16
A15-A8
X
D0H
X
Byte Program
10H
A23-A16
A15-A8
A7-A0
PD
X
Status Register
9FH
Reset
FFH
Definition for table 2:
1. X= don't care, H= number in hex.
2. A17-A23=don't care
3. PD= Program data
4. Reset Command is effective when the device is only in Erase or Program sequence (in tBP or tSE period).
SANYO Electric Co., Ltd.
2/9


Features omPreliminary Specifications CMOS LSI L E25FV101T t4U.c1M (128k words × 8bits ) Serial Flash EEPROM taSheeFeatures C MOS Flash EEPROM Technology aSingle 3.3 -Volt Read and Write Operations .DSecto r Erase Capability: 256 Bytes per secto r wOperating Frequency: 10MHz wLow Powe r Consumption w Active Current (Read): 25 mA (Max.) High Read/Write Reliabili ty Sector-write Endurance Cycles: 104 1 0 Years Data Retention Self-timed Erase and Programming Byte Programming: 35 s (Max.) End of Write Detection: Statu s Register Read Standby Current: 20 µ A (Max.) Serial Peripheral Interface (S .P.I.) mode 0. Hardware Data Protectio n Packages Available: MSOP8(225mil) .c omProduct Description Device Operation The LE25FV101T is a 128K x 8 CMOS sec tor Uerase, byte programmable serial Fl ash EEPROM. t4The LE25FV101T is manufac tured using SANYO's proprietary, high p erformance CMOS Flash eEEPROM technolog y. Breakthroughs in EEPROM cell design and process architecture attain better ereliability and manufactur.
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