Document
512Mb: x4, x8, x16 DDR SDRAM Features
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks
Features
•
VDD = VDD
2.5V ±0.2V, VDDQ = = 2.6V ±0.1V, VDDQ
2.5V ±0.2V = 2.6V ±0.1V
(DDR400)1
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
– 64ms, 8192-cycle
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported • tRAS lockout supported (tRAP = tRCD)
Options
Marking
• Configuration
– 128 Meg x 4 (32 Meg x 4 x 4 banks) – 64 Meg x 8 (16 Meg x 8 x 4 banks)
128M4 64M8
– 32 Meg x 16 (8 Meg x 16 x 4 banks) • Plastic package
32M16
– 66-pin TSOP
TG
– 66-pin TSOP (Pb-free) – 60-ball FBGA (10mm x 12.5mm) – 60-ball FBGA (10mm x 12.5mm) (Pb-free) – 60-ball FBGA (8mm x 12.5mm) – 60-ball FBGA (8mm x 12.5mm) (Pb-free) • Timing – cycle time
P FN2 BN2 CV3 CY3
– 5ns @ CL = 3 (DDR400) – 6ns @ CL = 2.5 (DDR333) (FBGA only) – 6ns @ CL = 2.5 (DDR333) (TSOP only)
-5B -62 -6T2
• Self refresh – Standard
None
– Low-power self refresh • Temperature rating
L
– Commercial (0°C to +70°C) – Industrial (–40°C to +85°C)
None IT
• Revision
– x4, x8, x16 – x4, x8, x16
:F :J
Notes: 1. DDR400 devices operating at < DDR333 conditions can use VDD/VDDQ = 2.5V +0.2V.
2. Available only on Revision F.
3. Available only on Revision J.
Table 1:
Key Timing Parameters CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3
Speed Grade
-5B -6 6T -75E/-75Z -75
CL = 2
133 133 133 133 100
Clock Rate (MHz)
CL = 2.5 167 167 167 133 133
CL = 3
200 n/a n/a n/a n/a
Data-Out Window
1.6ns 2.1ns 2.0ns 2.5ns 2.5ns
Access Window
±0.70ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns
DQS–DQ Skew
0.40ns 0.40ns 0.45ns 0.50ns 0.50ns
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a 512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM Features
Table 2: Addressing
Parameter Configuration Refresh count Row address Bank address Column address
128 Meg x 4
32 Meg x 4 x 4 banks 8K
8K (A0–A12) 4 (BA0, BA1) 4K (A0–A9, A11, A12)
64 Meg x 8
16 Meg x 8 x 4 banks 8K
8K (A0–A12) 4 (BA0, BA1) 2K (A0-A9, A11)
32 Meg x 16
8 Meg x 16 x 4 banks 8K
8K (A0–A12) 4 (BA0, BA1) 1K (A0–A9)
Table 3: Speed Grade Compatibility
Marking -5B1 -6 -6T -75E -75Z -75
PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) Yes Yes Yes Yes Yes Yes – Yes Yes Yes Yes Yes – Yes Yes Yes Yes Yes – – Yes Yes Yes Yes – – – Yes Yes Yes – – – – Yes Yes
-5B
-6/-6T
-75E
-75Z
-75
-75
Notes: 1. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is VDD = VDDQ = 2.5V ± 0.2V.
Figure 1: 512Mb DDR SDRAM Part Numbers
MT46V
Example Part Number: MT46V32M16P-6T:F
Configuration
-:
Package
Speed
Sp. Op.
Temp.
Revision
Configuration 128 Meg x 4 128M4 64 Meg x 8 64M8 32 Meg x 16 32M16
Package 400-mil TSOP 400-mil TSOP (Pb-free) 10mm x 12.5mm FBGA 10mm x 12.5mm FBGA (Pb-free) 8mm x 12.5mm FBGA 8mm x 12.5mm FBGA (Pb-free)
TG P FN BN CV CY
Revision :F x4, x8, x16 :J x4, x8, x16
Operating Temp Commercial
IT Industrial
Special Options Standard
L Low power
Speed Grade -5B tCK = 5ns, CL = 3 -6 tCK = 6ns, CL = 2.5 -6T tCK = 6ns, CL = 2.5
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: www.micron.com.
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a 512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM Table of Contents
Table of Contents
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..