CY7C09579V

1 7C09579V: 10/97 Revision: May 1, 2000 Features w w True dual-ported memory cells which allow simultaneous access of the same memory location Two Flow-Through/Pipelined devices — 16K x 36 organization (CY7C09569V) w .D a S a t e e h U 4 t . m o c PRELIMINARY CY7C09569V CY7C09579V 3.3V 16K/32K x 36 FLEx36™ Synchronous Dual-Port Static RAM 3.3V Low operating power — Active = 260 mA (typical) — Standby = 10 µA (typical) Fully synchronous interface for ease of use Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes Counter Address Read Back via I/O lines Single Chip Enable Automatic power-down Commercial and Industrial Temperature Ranges Compact package — 144-Pin TQFP (20 x 20 x 1.4 mm) — 172-Ball BGA (1.0 mm pitch) (15 x 15 x .51 mm) — 32K x 36 organization (CY7C09579V) 0.25-micron CMOS for optimum speed/power Three modes — Flow-Through — Pipelined — Burst Bus-Matching Capabilities on Right Port (x36 to x18 or x9) Byte-Select Capabilities on Left Port 133-MHz Pipelined Operation High-speed clock to data access 4.1/5/6/8 ns Logic Block Diagram R/WL OEL B0–B3 CEL FT/PipeL Left Port Control Logic 9 I/O0L–I/O 8L 9 I/O9L–I/O 17L I/O18L–I/O26L I/O27L–I/O35L A0–A13/14L CLKL ADSL CNTENL CNTRSTL [1] w 14/15 w 9 9 w .D t a S a e h t e U 4 Right Port Control Logic .c m o R/WR OER CER FT/PipeR BE 9 9 I/O Control I/O Control 9 9 Bus Match...