ICS9112-28

Integrated Circuit Systems, Inc. S a t General Description a The ICS9112-28 a high performance, low skew, low jitter .D It isisdesigned clock driver. to distribute high speed clocks in PC w systems operating at speeds from 0 to 133 MHz. w wThe ICS9112-28 comes in an eight pin 150 mil SOIC package. It has four output clocks. Block Diagram CLK0 CLK1 CLK_IN CLK2 CLK3 Low Skew h Output Buffer t e e 4U .c om ICS9112-28 Preliminary Product Preview Features Frequency range 0 - 133 MHz (3.3V) Less than 200 ps Jitter between outputs Skew controlled outputs Skew less than 250 ps between outputs Available in 8 pin 150 mil SOIC & 173 mil TSSOP packages. 3.3V ±10% operation Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME w CLK_IN CLK0 GND 1 w 1 1 w .D TYPE IN OUT PWR OUT OUT OUT PWR OUT t a CLK4 S a e h t e ICS9112-28 CLK_IN CLK0 GND U 4 1 2 3 4 Pin Configuration 8 7 6 5 CLK4 VDD CLK3 CLK2 .c m o CLK1 8 pin SOIC DESCRIPTION Input reference frequency. Buffered clock output Ground Buffered clock output Buffered clock output Buffered clock output Power Supply (3.3V) Buffered clock output CLK11 CLK21 CLK3 VDD CLK4 Notes: 1. Weak pull-down on all outputs 9112-28 Rev A 02/13/02 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. w w w .D at h S a t e e 4U . m o c ICS9112-28 Preliminary Prod...