PLL650-05

FEATURES w w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 3 fixed outputs of 25MHz, 75Mhz and 125Mhz with output disable SDRAM selectable frequencies of 105, 83.3, 140MHz (Double Drive Strength). Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% center for SDRAM and CPU. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. .D at h S a t e e 4U . m o c PLL650-05 Low EMI Network LAN Clock PIN CONFIGURATION XIN XOUT/ENB_125M*^ GND VDD 125MHz GND 75MHz/FS1*^ ENB_75MHz^ 1 2 16 15 VDD VDD 25MHz/FS0*^ GND GND SDRAMx2 VDD SS0T PLL 650-05 3 4 5 6 7 8 14 13 12 11 10 9 Note: SDRAMx2: Double Drive strength. T: Tri-Level input ^: Internal pull-up resistor *: Bi-directional pin (input value is latched upon power-up). DESCRIPTIONS The PLL 650-05 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. BLOCK DIAGRAM XIN XOUT XTAL OSC w w w .D t a S a e h FS1 0 1 1 0 FREQUENCY TABLE FS0 0 1 0 1 SDRAMX2 Tristate 140MHz SST 83.3MHzSST 105MHzSST t e U 4 .c m o 1 125MHz (can be disabled) 1 Control Logic 1 SDRAM (105, 83.3...