Low Phase Noise XO
m Preliminary PLL620-00 o c . XO with multipliers (for HF Fund. and 3 O.T.) Low Phase Noise U t4 e FEATURES DIE CONFIGUR...
Description
m Preliminary PLL620-00 o c . XO with multipliers (for HF Fund. and 3 O.T.) Low Phase Noise U t4 e FEATURES DIE CONFIGURATION e h S Fundamental Mode Crystal. 100MHz to 200MHz a Output range: – 200MHz (no multiplication), at 100 200 – 400MHz (2x multiplier) or 400 – 700MHz (4x.D multiplier). w High yield design support up to 2pF string capacitance at 200MHz. w Available outputs: PECL, LVDS, or CMOS. w Supports 3.3V-Power Supply.
rd
65 mil (1550,1475)
25 24 23 22 21 20 19 18 17 26 16 27 15 28 14
Available in die form. Thickness 10 mil.
DESCRIPTIONS
PLL620-00 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring LVDS or PECL output levels at high frequencies.
BLOCK DIAGRAM
SEL
Vin X+ XOscillator Amplifier
m o .c U 4 t e e h S a t a .D w w w
62 mil
13 29 12 11 30 10 9 31 1 2 3 4 5 6 7 8
Y
(0,0)
X
DIE SPECIFICATIONS
Name Size Reverse side
Value
62 x 65 mil GND
Pad dimensions Thickness
80 micron x 80 micron 10 mil
OUTPUT SELECTION AND ENABLE
Pad #18 OUTSEL1 0 0 1 1 Pad #25 OUTSEL0 0 1 0 1 Selected Output
OE Q
PLL (Phase Locked Loop)
Q
High Drive CMOS Standard CMOS LVDS PECL (default) State
PLL by-pass
PLL620-00
OE_SELECT (Pad #9) 0
1 (Default)
Pad #9...
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