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PLL620-07 Dataheets PDF



Part Number PLL620-07
Manufacturers PhaseLink
Logo PhaseLink
Description (PLL620-05/06/07/08/09) Low Phase Noise XO
Datasheet PLL620-07 DatasheetPLL620-07 Datasheet (PDF)

m PLL620-05/-06/-07/-08/-09 o c . XO with multipliers (for 120-200MHz Fund Xtal) Low Phase Noise U Universal Low Phase Noise IC’s 4 t e e FEATURES h PIN CONFIGURATION S (Top View) a200MHz Fundamental Mode Crystal. • 120MHz to t • Output a range: 120 – 200MHz (no multiplication), D 240 – 400MHz (2x multiplier) or 480 – 700MHz . (4x multiplier). w •w High yield design support up to 2pF string at 200MHz. w• capacitance CMOS (Standard drive PLL620-07 or Selectable VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 .

  PLL620-07   PLL620-07


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m PLL620-05/-06/-07/-08/-09 o c . XO with multipliers (for 120-200MHz Fund Xtal) Low Phase Noise U Universal Low Phase Noise IC’s 4 t e e FEATURES h PIN CONFIGURATION S (Top View) a200MHz Fundamental Mode Crystal. • 120MHz to t • Output a range: 120 – 200MHz (no multiplication), D 240 – 400MHz (2x multiplier) or 480 – 700MHz . (4x multiplier). w •w High yield design support up to 2pF string at 200MHz. w• capacitance CMOS (Standard drive PLL620-07 or Selectable VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND XIN • • GND/ DRIVSEL* Drive PLL620-06), PECL (Enable low PLL620-08 or Enable high PLL620-05) or LVDS output (PLL620-09). Supports 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL620-06 only available in 3x3mm. Note: PLL620-07 only available in TSSOP. DESCRIPTIONS GND GND GND BLOCK DIAGRAM SEL ^: Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) OE Q Q X+ X- Oscillator Amplifier PLL (Phase Locked Loop) OUTPUT ENABLE LOGICAL LEVELS Part # PLL620-08 PLL620-05 PLL620-06 PLL620-07 PLL620-09 PLL by-pass OE input: Logical states defined by PECL levels for PLL620-08 Logical states defined by CMOS levels for PLL620-05/-06/-07/-09 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 m o .c U 4 t e e h S a at .D w w w 1 (Default) Output enabled Rev 10/29/02 Page 1 OE 0 (Default) 1 0 State Output enabled Tri-state Tri-state GND PLL620-05/-06/-07/-08/-09 are XO IC specifically designed to pull high frequency fundamental crystals. Their design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. m o .c U 4 t e e h S a t a .D w w w XOUT SEL3^ SEL2^ OE GND GND SEL0^ XIN 12 11 10 9 SEL1^ VDD PLL 620-0x CLKC VDD CLKT GND GND 13 8 7 6 5 GND CLKC VDD CLKT XOUT 14 15 PLL620-0x 1 2 3 SEL2^ OE 16 4 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal) PIN DESCRIPTIONS Name XIN XOUT OE GND DRIVSEL** Universal Low Phase Noise IC’s TSSOP* Pin number 2 3 6 7,8,9, 10, 14 - 3x3mm QFN* Pin number 13 14 16 1,2,3,4,8,12 12 Type I I I P I Crystal in connector. Crystal out connector. Output enable pin. Description GND (except pin 12 on PLL620-06: DRIVSEL see below). PLL620-06 only: Drive Select Input. This pin has an internal pullup that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL620-06 will be high drive CMOS when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise. True output PECL (PLL620-08) or LVDS (PLL620-09) (N/C for PLL620-07) Complementary output PECL (PLL620-08) or LVDS (PLL620-09) (CMOS out for PLL620-07). CLKT CLKC SEL0 SEL1 SEL2 SEL3 VDD 11 13 5 7 10 9 15 Not available 6,11 O O 16 15 5 4 1, 12 I I I I P +3.3V VDD. Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. * Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL620-06 only. FREQUENCY SELECTION TABLE SEL3 1 1 1 SEL2 0 1 1 SEL1 1 1 1 SEL0 1 0 1 Selected Multiplier Fin x 4 Fin x 2 No multiplication Note: SEL3 is not available (always “1”) in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/29/02 Page 2 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Universal Low Phase Noise IC’s SYMBOL V DD VI VO TS TA TJ MIN. V SS -0.5 V SS -0.5 -65 -40 MAX. 7 V DD +0.5 V DD +0.5 150 85 125 260 2 UNITS V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only. 2. Crystal Specifications PARAMETERS Built-in Capacitance Inter-electrode capacitance Oscillation Frequency SYMBOL CX+ CXC0 OF CONDITIONS 120MHz to 200MHz (VDD=3.3V) Fund. MIN. MAX. 2 2 2 UNITS pF 120 200 MHz 3. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL I DD V DD CONDITIONS PECL/.


PLL620-06 PLL620-07 PLL620-08


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