PLL650-02

m o .c U 4 t e FEATURES e h Full CMOS output swing with 40-mA output drive S output capability. 25-mA drive at TTL level. a t Advanced, low power, sub-micron CMOS processes. a 25MHz .D fundamental crystal or clock input. 4 outputs at 50MHz, 2 outputs selectable at 25MHz or w 125MHz, 1 output selectable at 25MHz or 100MHz. w SDRAM selectable frequencies of 66.6, 75, 83.3, w 2 100MHz (Double Drive Strength). PLL650-02 Low EMI Network LAN Clock PIN CONFIGURATION VDD XIN XOUT/50MHz_OE*^ GND VDD 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 VDD VDD 25MHz/100MHz GND SDRAMx2 GND All non SDRAM outputs can be disabled (tri-state) Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% for SDRAM and 100MHz output. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 24-Pin 150mil SSOP. DESCRIPTIONS The PLL 650-02 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25 MHz crystal, and produces multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs, with double drive strength for its SDRAM outputs. BLOCK DIAGRAM XIN XOUT XTAL OSC m o .c U 4 t e e h S a t a .D w w w 50MHz/FS0*^ GND 50MHz/FS1*^ 50MHz/FS2*T FS3T 10 11 12 50MHz/SS0*T VDD Note: SDRAMx2: Double Drive strength. T: Tri-Level input ^: Internal pull-up resistor. *: Bi-directional pin (input value is latched upon pow...