PLL600-17

FEATURES w w w Low phase noise (-130 dBc @ 10kHz offset). CMOS output with OE tri-state control. Selectable oscillator “on” or “off” feature in output disable mode Ultra Low current consumption (<2.5mA, <2mA, <1.3mA at 27MHz respectively for PLL600-17, PLL600-27, and PLL600-37) Ultra Low disable mode current (<2uA when disabled with osc. off) 10 to 52MHz fundamental crystal input. Selectable divider by 2 (PLL600-17 only). 12mA drive capability at TTL output. Low jitter (RMS): 2.5ps period jitter. 2.25V to 3.63V DC operation. Available in 8 pin SOIC, 6 pin SOT or DIE. .D at h S a t e e Ultra Low Current XO (Crystals from 10 MHz to 52 MHz) PIN ASSIGNMENT (PACKAGE) 8 pin SOIC XIN SEL*^ GND OSCSEL^ * Note: ^: 4U . m o c Preliminary PLL600-17/-27/-37 1 2 3 4 8 7 6 5 XOUT OE^ VDD CLK pin2 is SEL for PLL600-17 pin2 is N/C for PLL600-27/-37 denotes internal pull-up 6 pin SOT CLK DESCRIPTION The PLL600-17/-27/-37 form a low cost family of XO IC’s, designed to consume the lowest current on the market for the 5MHz to 52MHz range. It accepts input crystal from 10 to 52MHz (fundamental resonant mode) and offers a selectable divider by 2 (PLL600-17 only) or no division. Providing less than -130dBc at 10kHz offset at 30MHz, and with a very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring low current frequency sources, such as handheld devices. BLOCK DIAGRAM SEL Reference Divider XIN XOUT XTAL OSC w w w OE ...