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PLL601-01 Dataheets PDF



Part Number PLL601-01
Manufacturers PhaseLink
Logo PhaseLink
Description Low Phase Noise PLL Clock Multiplier
Datasheet PLL601-01 DatasheetPLL601-01 Datasheet (PDF)

m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or • Reference a clock. .D crystal load capacitor: no external • Integrated w load capacitor required. w • Output clocks up to 160MHz at 3.3V. w• Low phase noise. • • • • • Output Enable function tri-state outputs. Low jitter: Less than 60 ps cycle to cycle. Advanced, low power, sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. Preliminary.

  PLL601-01   PLL601-01


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m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or • Reference a clock. .D crystal load capacitor: no external • Integrated w load capacitor required. w • Output clocks up to 160MHz at 3.3V. w• Low phase noise. • • • • • Output Enable function tri-state outputs. Low jitter: Less than 60 ps cycle to cycle. Advanced, low power, sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier PIN CONFIGURATION CLK REFEN VDD VDD VDD 1 2 16 15 GND GND GND REFOUT OE S0 S3 S2 PLL 601-01 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTIONS The PLL601-01 is a low cost, high performance and low phase noise clock synthesizer. With PhaseLink’s proprietary analog and digital Phase Locked Loop techniques, the chip accepts 10-27MHz crystal or clock input, and produces outputs clocks up to 160MHz at 3.3V. BLOCK DIAGRAM S3 S2 S1 S0 m o .c U 4 t e e h S a t a .D w w w XOUT S1 XIN ROM Based Multipliers VCO Divider Reference Divider Phase Comparator Charge Pump Loop Filter VCO OE XIN XOUT XTAL OSC REFEN 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 m o .c U 4 t e e h S a at .D w w w CLK REFOUT Rev 10/12/00 Page 1 Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier PIN DESCRIPTIONS Name CLK REFEN VDD XIN XOUT OE REFOUT S0 S1 S2 S3 GND Number 1 2 3,4,5 8 6 12 13 11 7 9 10 14,15,16 Type O I P I O I O I I I I P Description Clock output from VCO. Equals the input frequency times multiplier. Reference clock enable. When Low, it turns off REFOUT. 3.3V Power Supply. Crystal input to be connected to 10-27MHz fundamental parallel mode crystal (C L =18pF). On chip load capacitors: No external capacitor required. Crystal Connection. Output Enable. Tri-state CLK and REFOUT when low. Has internal pull-up. Buffered crystal oscillator clock output. Controlled by REFEN. Multiplier Select Pin 0. Determines CLK output. Has internal pull-up. Multiplier Select Pin 1. Determines CLK output. Has internal pull-up. Multiplier Select Pin 2. Determines CLK output. Has internal pull-up. Multiplier Select Pin 3. Determines CLK output. Has internal pull-up. Ground. MULTIPLIER SELECT TABLE S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK Test Input x 11 Input x 1 Input x 3 Input x 4 Input x 5 Input x 6 Input x 8 Input x 7 Crystal Oscillator Frequency Pass through Input x 2 Input x 9 Input x 8 Input x 10 Input x 12 Input x 16 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/12/00 Page 2 Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature Storage Temperature Ambient Operating Temperature TS -65 0 SYMBOL V CC VI VO MIN. MAX. 7 V CC + 0.5 V CC + 0.5 260 150 70 UNITS V V V °C °C °C - 0.5 - 0.5 - 0.5 Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC Specification PARAMETERS Input Frequency Output Frequency Output Rise Time Output Fall Time Duty Cycle Max. Absolute Jitter Max. Jitter, cycle to cycle Phase Noise, relative to carrier, 125Mhz(x5) Phase Noise, relative to carrier, 125Mhz(x5) Phase Noise, relative to carrier, 125Mhz(x5) Phase Noise, relative to carrier, 125Mhz(x5) Note: *: To be measured. CONDITIONS At 3.3V 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 Short term 100 Hz offset, 3.3V 1kHz offset, 3.3V 10kHz offset, 3.3V 100kHz offset, 3.3V MIN. 10 TYP. MAX. 27 160 1.5 1.5 UNITS MHz MHz ns ns % ps ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz 45 50 ± 100 55 60 * * * * 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/12/00 Page 3 Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier 3. DC Specification PARAMETERS Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Operating Supply Current Short-circuit Current Input Capacitance SYMBOL VDD V IH V IL V IH V IL V OH V OL V OH I DD IS C IN CONDITIONS MIN. 3.135 2 TYP. MAX. 3.465 0.8 UNITS V V V V V V V V For XIN pin For XIN pin I OH = -25mA I OL = 25mA I OH = -8mA No Load OE, Select Pins (VDD/2) + 1 2.4 VDD/2 VDD/2 (VDD/2) − 1 0.4 VDD-0.4 35 ± 120 5 mA mA pF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/12/00 Page 4 Preliminary PLL601-01.


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