PLL601-01

m o .c U 4 t e FEATURES e h Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or Reference a clock. .D crystal load capacitor: no external Integrated w load capacitor required. w Output clocks up to 160MHz at 3.3V. w Low phase noise. Output Enable function tri-state outputs. Low jitter: Less than 60 ps cycle to cycle. Advanced, low power, sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier PIN CONFIGURATION CLK REFEN VDD VDD VDD 1 2 16 15 GND GND GND REFOUT OE S0 S3 S2 PLL 601-01 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTIONS The PLL601-01 is a low cost, high performance and low phase noise clock synthesizer. With PhaseLink’s proprietary analog and digital Phase Locked Loop techniques, the chip accepts 10-27MHz crystal or clock input, and produces outputs clocks up to 160MHz at 3.3V. BLOCK DIAGRAM S3 S2 S1 S0 m o .c U 4 t e e h S a t a .D w w w XOUT S1 XIN ROM Based Multipliers VCO Divider Reference Divider Phase Comparator Charge Pump Loop Filter VCO OE XIN XOUT XTAL OSC REFEN 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 m o .c U 4 t e e h S a at .D w w w CLK REFOUT Rev 10/12/00 Page 1 Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier PIN DESCRIPTIONS Name CLK REFEN VDD XIN XOUT OE REFOUT S0 S1 S2 S3 GND Number 1 2 3,4,5 8 6 12 13 11 7 9 10 14,15,16 Type O ...