.comFeatures
U• 3.0V to 3.6V Read/Write
t4• Burst Read Performance
e– <100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time
etSAC = 7 ns
h– <75 MHz (RAS Latency = 2, CAS Latency = 5), 13 ns Cycle Time
StSAC = 8 ns
ta– <50 MHz (RAS Latency = 1, CAS Latency = 4), 20 ns Cycle Time
atSAC = 9 ns
• MRS Cycle with Address Key Programs
.D– RAS Latency (1 and 2)
w 32-megabit– CAS Latency (2 ~ 8)
w– Burst Length: 4, 8
(1M x 32 or– Burst Type: Sequential and Interleaved
w• Word Selectable Organization
2M xm16)– 16 (Word Mode)/x 32 (Double Word Mode)
• Sector Erase Architecture
Higoh-speed– Eight 256K Word or 128K Double Word (4-Mbit) Sectors
.Sc• Independent Asynchronous Boot Block
ynchronous– 8K x 16 Bits with Hardware Lockout
• Fast Program Time
– 3-volt, 100 µs per Word/Double Word Typical
U Flash Memory– 12-volt, 30 µs per Word/Double Word Typical
t4• Fast Sector Erase Time
– 2.5 Seconds at 3 Volts
– 1.6 Seconds at 12 Volts
e AT49LD3200• Low-power Operation
– ICC Read = 75 mA Typical
e AT49LD3200B• Input and Output Pin Continuity Test Mode Optimizes Off-board Programming
• Package:
h SFlash– 86-pin TSOP Type II with Off-center Parting Line (OCPL) for Improved Reliability
• LVTTL-compatible Inputs and Outputs
taSDescription
The AT49LD3200 or AT49LD3200B SFlash™ is a synchronous, high-bandwidth Flash
amemory fabricated with Atmel’s high-performance CMOS process technology and is
organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double
.Dword mode), depending on the polarity of the WORD pin (see Pin Function Descrip-
tion Table). Synchronous design allows precise cycle control. I/O transactions are
possible on every clock cycle. All operations are synchronized to the rising edge of the
wsystem clock. The range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high-band-
wwidth, high-performance memory system applications.
mThe AT49LD3200B will automatically activate the Asynchronous Boot Block after
w opower-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be acti-
.cvated through Mode Register Set.
UThe synchronous DRAM interface allows designers to maximize system performance
t4while eliminating the need to shadow slow asynchronous Flash memory into high-
espeed RAM.
eThe 32-megabit SFlash device is designed to sit on the synchronous memory bus and
www.DataShoperate alongside SDRAM.
™
Rev. 1940B–11/01
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