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Flash Memory. AT49LD3200B Datasheet |
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.comFeatures
U• 3.0V to 3.6V Read/Write
t4• Burst Read Performance
e– <100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time
etSAC = 7 ns
h– <75 MHz (RAS Latency = 2, CAS Latency = 5), 13 ns Cycle Time
StSAC = 8 ns
ta– <50 MHz (RAS Latency = 1, CAS Latency = 4), 20 ns Cycle Time
atSAC = 9 ns
• MRS Cycle with Address Key Programs
.D– RAS Latency (1 and 2)
w 32-megabit– CAS Latency (2 ~ 8)
w– Burst Length: 4, 8
(1M x 32 or– Burst Type: Sequential and Interleaved
w• Word Selectable Organization
2M xm16)– 16 (Word Mode)/x 32 (Double Word Mode)
• Sector Erase Architecture
Higoh-speed– Eight 256K Word or 128K Double Word (4-Mbit) Sectors
.Sc• Independent Asynchronous Boot Block
ynchronous– 8K x 16 Bits with Hardware Lockout
• Fast Program Time
– 3-volt, 100 µs per Word/Double Word Typical
U Flash Memory– 12-volt, 30 µs per Word/Double Word Typical
t4• Fast Sector Erase Time
– 2.5 Seconds at 3 Volts
– 1.6 Seconds at 12 Volts
e AT49LD3200• Low-power Operation
– ICC Read = 75 mA Typical
e AT49LD3200B• Input and Output Pin Continuity Test Mode Optimizes Off-board Programming
• Package:
h SFlash– 86-pin TSOP Type II with Off-center Parting Line (OCPL) for Improved Reliability
• LVTTL-compatible Inputs and Outputs
taSDescription
The AT49LD3200 or AT49LD3200B SFlash™ is a synchronous, high-bandwidth Flash
amemory fabricated with Atmel’s high-performance CMOS process technology and is
organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double
.Dword mode), depending on the polarity of the WORD pin (see Pin Function Descrip-
tion Table). Synchronous design allows precise cycle control. I/O transactions are
possible on every clock cycle. All operations are synchronized to the rising edge of the
wsystem clock. The range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high-band-
wwidth, high-performance memory system applications.
mThe AT49LD3200B will automatically activate the Asynchronous Boot Block after
w opower-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be acti-
.cvated through Mode Register Set.
UThe synchronous DRAM interface allows designers to maximize system performance
t4while eliminating the need to shadow slow asynchronous Flash memory into high-
espeed RAM.
eThe 32-megabit SFlash device is designed to sit on the synchronous memory bus and
www.DataShoperate alongside SDRAM.
™
Rev. 1940B–11/01
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Pin Configuration
To maximize system manufacturing throughput the AT49LD3200(B) features high-
speed 12-volt program and erase options. Additionally, stand-alone programming cycle
time of individual devices or modules is optimized with Atmel’s unique input and output
pin continuity test mode.
VCC
DQ0
VCCQ
DQ16
DQ1
VSSQ
DQ17
DQ2
VCCQ
DQ18
DQ3
VSSQ
DQ19
MR
VCC
DQM
NC
CAS
RAS
CS
WORD
A12
A11
A10
A0
A1
A2
NC
VCC
NC
DQ4
VSSQ
DQ20
DQ5
VCCQ
DQ21
DQ6
VSSQ
DQ22
DQ7
VCCQ
DQ23
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
TSOP (Type II)
Top View
86 VSS
85 DQ31
84 VSSQ
83 DQ15
82 DQ30
81 VCCQ
80 DQ14
79 DQ29
78 VSSQ
77 DQ13
76 DQ28
75 VCCQ
74 DQ12
73 NC
72 VSS
71 NC
70 VPP
69 WE
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 NC
58 VSS
57 NC
56 DQ27
55 VCCQ
54 DQ11
53 DQ26
52 VSSQ
51 DQ10
50 DQ25
49 VCCQ
48 DQ9
47 DQ24
46 VSSQ
45 DQ8
44 VSS
2 AT49LD3200(B)
1940B–11/01
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AT49LD3200(B)
Pin Function Description
Pin
CLK
CS
CKE
A0 - A12
RAS
CAS
MR
DQ0 - DQ31
VCC/VSS
VCCQ/VSSQ
WORD
DQM
NC
WE
VPP
Name
System Clock
Chip Select
Clock Enable
Address
Row Address Strobe
Column Address Strobe
Mode Register Set
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
x32/x16 Mode Selection
Data-out Masking
No Connection
Write Enable
Program/Erase Pin Supply
Input Function
Active on the rising edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK and CKE.
Masks system clock to freeze operation from the next clock cycle. CKE should be
enabled at least one cycle prior to new command. Disables input buffers for power-
down in standby mode.
Row/column addresses are multiplexed on the same pins.
Row address: RA0 ~ RA12, Column address: CA0 ~ CA6 (x32), CA0 ~ CA7 (x16)
Latches row addresses on the rising edge of the CLK with RAS low.
Enables row access.
Latches column addresses on the rising edge of the CLK with CAS low.
Enables column access.
Enables mode register set with MR low. (Simultaneously CS, RAS and CAS are low).
Data input for program/erase. Data output for read.
Power and ground for the input buffers and the core logic.
Power and ground for the output buffers.
Double word mode/word mode, depending on polarity of WORD pin (WORD = high,
double word mode; WORD = low, word mode).
Should be set to the desired state during power-up and prior to any device operation.
Masks output operation when a complete burst is not required.
Not connected
Enables the chip to be written.
Program/Erase power supply.
1940B–11/01
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