XCR5128

APPLICATION NOTE DS041 (v1.2) August 10, 2000 Features w w Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed IEEE 1149.1-compliant, JTAG Testing Capability - Four pin JTAG interface (TCK, TMS, TDI, TDO) - IEEE 1149.1 TAP Controller - JTAG commands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ 5V, In-System Programmable (ISP) using the JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms High speed pin-to-pin delays of 7.5 ns Ultra-low static power of less than 100 µA 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Four clocks available Programmable clock polarity at every macrocell Support for asynchronous clocking Innovative XPLA™ architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms PCI compliant Advanced 0.5µ E2CMOS process Security bit prevents unauthorized access Design entry and verification using industry standard and Xilinx CAE tools Reprogrammable using industry standard device programmers Innovative Control Term structure provides either sum terms or product terms in each logic block for: - ...