UPD44165182

DATA SHEET MOS INTEGRATED CIRCUIT µPD44165082, 44165182, 44165362 18M-BIT QDRTMII SRAM 2-WORD BURST OPERATION Description The µPD44165082 is a 2,097,152-word by 8-bit, the µPD44165182 is a 1,048,576-word by 18-bit and the µPD44165362 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44165082, µPD44165182 and µPD44165362 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA. Features 1.8 ± 0.1 V power supply and HSTL I/O DLL circuitry for wide output data valid window and future frequency scaling Separate independent read and write data ports with concurrent transactions 100% bus utilization DDR READ and WRITE operation Two-tick burst for low DDR transaction size Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device Internally self-timed write control Clock-stop capability with µs restart User programmable impedance output Fast clock cycle time : 5.0 ns (200 MHz), 6.0 ns ...