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PCI6254 Dataheets PDF



Part Number PCI6254
Manufacturers PLX Technology
Logo PLX Technology
Description Dual Mode PCI to PCI Bridge
Datasheet PCI6254 DatasheetPCI6254 Datasheet (PDF)

w w a D . w S a t e e h U 4 t m o .c PCI 6254 (HB6) Dual Mode Universal PCI-to-PCI Bridge Data Book w w .D w t a S a e h t e U 4 .c m o w w w .D a S a t e e h U 4 t m o .c PCI 6254 (HB6) Dual Mode Universal PCI-to-PCI Bridge Data Book Version 2.1 December 2003 Website: http://www.plxtech.com Technical Support: http://www.plxtech.com/support Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169 © 2003 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retain.

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w w a D . w S a t e e h U 4 t m o .c PCI 6254 (HB6) Dual Mode Universal PCI-to-PCI Bridge Data Book w w .D w t a S a e h t e U 4 .c m o w w w .D a S a t e e h U 4 t m o .c PCI 6254 (HB6) Dual Mode Universal PCI-to-PCI Bridge Data Book Version 2.1 December 2003 Website: http://www.plxtech.com Technical Support: http://www.plxtech.com/support Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169 © 2003 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are property of their respective owners. This device is not designed, intended, authorized, or warranted to be suitable for use in medical, life-support applications, devices or systems or other critical applications. PLX Part Number: PCI 6254-AB66BC; Former HiNT Part Number: HB6 Order Number: 6254-SIL-DB-P1-2.0 Printed in the USA, May 2003 PCI 6254 Dual-Mode Universal PCI-to-PCI Bridge Adaptive High Performance Asynchronous 66MHz 64-bit PCI-to-PCI Bridge for Servers, Storage, Telecommunication, Networking and Embedded Applications PLX’s latest PCI 6254 64-bit PCI-to-PCI bridge is designed for high performance, high availability applications in bus expansions, programmable data transfer rate control, frequency conversions from slower PCI to faster PCI or from faster PCI to slower PCI buses, address remapping, high availability Hot Swap enabling and universal system-to-system bridging. PCI 6254 has sophisticated buffer management and buffer configuration options designed to provide customizable performance optimization. • • • • • • • • • • • • • • • • • • • PCI Local Bus Specification Rev 2.3 support High speed PCI buffer supports 3.3V signaling with 5V input signal tolerance CPCI Hot Swap Specification PICMG 2.1 R2.0 with PI = 1 support Device Hiding support eliminates mid-transaction extraction problems Programmable 32 bit to 64 bit access conversion. Programmable Address Translation to Secondary Bus Flow-Through 0 wait state burst up to 4K bytes for optimal large volume data transfer Supports up to 4 simultaneous posted write transactions and 4 simultaneous Delayed transactions in each direction Provides 1K Bytes of buffering 256 byte upstream posted write buffer 256 byte downstream posted write buffer 256 byte upstream read data buffer 256 byte downstream read data buffer Programmable prefetch amount of up to 256 bytes for maximum read performance optimization Supports out of order delayed transactions Support Secondary Port PCI Private Memory Space Option to eliminates possible dead lock on PCI-VME bridges before or behind PCI 6254 • • • • Serial EEPROM loadable and programmable PCI READ ONLY Register configurations. External arbiter or programmable arbitration for 9 bus masters on secondary interface support 10 Secondary clock outputs with pin controlled enable and individual maskable control PCI Mobile Design Guide and Power Management D3 Cold Wakeup capable with PME# support 16 GPIO pins with output control and 8 are with power up status latch capabilities Enhanced address decoding Support 32-bit I/O address range 32-bit memory-mapped I/O address range ISA aware mode for legacy support in the first 64KB of I/O address range VGA addressing and palette snooping support Provides an IEEE standard 1149.1 JTAG interface for boundary scan test Asynchronous design supports standard 66Mhz to 33MHz and faster secondary port speed such as 33Mhz to 66MHz conversion PCI 6254 package ball layout is super set of PLX PCI 6154 and Intel 21154 when operating in Transparent Mode Industry standard 31mm x 31mm 365-ball PBGA package PCI 6254 Non-Transparent and Universal Mode Features • • • • • • • • • • • • • • • Programmable Transparent, Non-Transparent or Universal Mode operation Jumper less switching between System and Peripheral Slot applications in CPCI Programmable Primary or Secondary Port System boot up priority. Semaphore backed Cross-bridge Configuration Space access Powerful multi-source (Direct encoded, door bell, PCI Reset, external pin) programmable interrupts Message Interrupt Support Optional power up 16M memory space claim to avoid Initially Retry or Initially Not Respond requirement Behave as a Memory mapped PCI device Primary and Secondary Port controllable GPIOs Power-Good input Available Primary and Secondary Power Status inputs for port power detection Independent Primary and Secondary Port Reset inputs Configurable Primary and Secondary Reset Outputs Sticky user registers immune to PCI resets Supporting up to 9 secondary PCI master devices PCI 6254 Data Book v2.1  2003 PLX Technology, Inc. All rights reserved. 5 HISTORY Rev Rev 0.1 .


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