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BU-6186x Dataheets PDF



Part Number BU-6186x
Manufacturers Data Device
Logo Data Device
Description Enhanced Miniature Advanced Communications Engine
Datasheet BU-6186x DatasheetBU-6186x Datasheet (PDF)

BU-6174X/6184X/6186X ENHANCED MINIATURE ADVANCED COMMUNICATIONS ENGINE [ENHANCED MINI-ACE/µ-ACE (MICRO-ACE)] FEATURES Make sure the next Card you purchase has... ® • Fully Integrated 1553A/B Notice 2, McAir, STANAG 3838 Interface Terminal • Compatible with Mini-ACE (Plus) and ACE Generations • Choice of : - RT or BC/RT/MT In Same Footprint - RT or BC/RT/MT with 4K RAM - BC/RT/MT with 64K RAM, and RAM parity • Choice of 5V or 3.3V Logic • Package Options: - 1" Square Ceramic Flat Pack or Gull.

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BU-6174X/6184X/6186X ENHANCED MINIATURE ADVANCED COMMUNICATIONS ENGINE [ENHANCED MINI-ACE/µ-ACE (MICRO-ACE)] FEATURES Make sure the next Card you purchase has... ® • Fully Integrated 1553A/B Notice 2, McAir, STANAG 3838 Interface Terminal • Compatible with Mini-ACE (Plus) and ACE Generations • Choice of : - RT or BC/RT/MT In Same Footprint - RT or BC/RT/MT with 4K RAM - BC/RT/MT with 64K RAM, and RAM parity • Choice of 5V or 3.3V Logic • Package Options: - 1" Square Ceramic Flat Pack or Gull Wing - 0.815" Square BGA (µ-ACE) DESCRIPTION The Enhanced Miniature Advanced Communications Engine (Enhanced Mini-ACE) and µ-ACE (Micro-ACE) family of MIL-STD-1553 terminals provide complete interfaces between a host processor and a 1553 bus, and integrate dual transceiver, protocol logic, and 4K or 64K words of RAM. At 0.815" square, the µ-ACE (BGA package) option provides the smallest footprint in the industry. The terminals are powered by a choice of 5V or 3.3V logic. Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, including versions incorporating McAir compatible transmitters, is provided. There is a choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT versions with 64K words of RAM include built-in RAM parity checking. BC features include a built-in message sequence control engine, with a set of 20 instructions. This feature provides an autonomous means of implementing multi-frame message scheduling, message retry schemes, data double buffering, asynchronous message insertion, and reporting to the host CPU. The Enhanced Mini-ACE/µ-ACE incorporates a fully autonomous built-in self-test, providing comprehensive testing of the internal protocol logic and/or RAM. The RT offers the same choices of subaddress buffering as the ACE and Mini-ACE (Plus), along with a global circular buffering option, 50% rollover interrupt for circular buffers, an interrupt status queue, and an "Auto-boot" option to support MIL-STD-1760. The terminals provide the same flexibility in host interface configurations as the ACE/Mini-ACE, along with a reduction in the host processor's worst case holdoff time. Most software features are compatible with the previous generations of the Mini-ACE (Plus) and ACE series. • 5V Transceiver with 1760 and McAir Compatible Options • Comprehensive Built-In Self-Test • Flexible Processor/Memory Interface, with Reduced Host Wait Time • Choice of 10, 12, 16, or 20 MHz Clock • Highly Autonomous BC with Built-In Message Sequence Control: - Frame Scheduling - Branching - Asynchronous Message Insertion - General Purpose Queue - User-defined Interrupts • Advanced RT Functions - Global Circular Buffering - Interrupt Status Queue - 50% Circular Buffer Rollover Interrupts • Selective Message Monitor - Selection by Address, T/R Bit, Subaddress - Command and Data Stacks - 50% and 100% Stack Rollover Interrupts FOR MORE INFORMATION CONTACT: µ-ACE Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com Technical Support: 1-800-DDC-5757 ext. 7771 © 2000 Data Device Corporation Data Device Corporation www.ddc-web.com CH. A CH. B TX/RX_A SHARED RAM (1) TRANSCEIVER A DATA BUFFERS PROCESSOR DATA BUS TX/RX_A DATA BUS DUAL ENCODER/DECODER, MULTIPROTOCOL AND MEMORY MANAGEMENT D15-D0 TX/RX_B ADDRESS BUS ADDRESS BUFFERS A15-A0 PROCESSOR ADDRESS BUS TRANSCEIVER B 2 TX/RX_B PROCESSOR AND MEMORY INTERFACE LOGIC TRANSPARENT/BUFFERED, STRBD, SELECT, RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN, MSB/LSB/DTGRT IOEN, READYD ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR, 8/16-BIT/DTREQ, POLARITY_SEL/DTACK INT PROCESSOR AND MEMORY CONTROL INTERRUPT REQUEST RT ADDRESS RTAD4-RTAD0, RTADP INCMD/MCRST, INCMD(2), MCRST(2) MISCELLANEOUS CLK_IN, TAG_CLK(2), MSTCLR, SSFLAG/EXT_TRG, TX-INH_A, TX-INH_B, UPADDREN, RSBITEN(2) NOTE 1: See Ordering Information for Available Memory Options. NOTE 2: Indicates signals brought out only on µ-ACE (BGA package) version. BU-6174X/6184X/6186X M-12/04-0 FIGURE 1. ENHANCED MINIATURE ADVANCED COMMUNICATIONS ENGINE BLOCK DIAGRAM TABLE 1. ENHANCED MINI-ACE/µ-ACE SERIES SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage • Logic +5V or +3.3V • RAM +5V • Transceiver +5V (Note 12) Logic • Voltage Input Range for +5V Logic (BU-61XX0/5) • Voltage Input Range for +3.3V Logic (BU-61XX0/3/5) RECEIVER Differential Input Resistance (Notes 1-6) Differential Input Capacitance (Notes 1-6) Threshold Voltage, Transformer Coupled, Measured on Stub Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage • Direct Coupled Across 35 Ω, Measured on Bus • Transformer Coupled Across 70 Ω, Measured on Bus (BU-61XXXXX-XX0, BU-61XXXXX-XX2) (Note 13) Output Noise, Diff (Direct Coupled) Output Offset Voltage, Transformer Coupled Across 70 ohms Rise/Fall Time (BU-61XXXX3, BU-61XXXX4) LOGIC VIH All signals except CLK_IN CLK_IN VIL All signals except CLK_IN CLK_IN Schmidt Hysteresis All signals except CLK_IN CLK_IN IIH, IIL All signals except CLK_IN IIH (Vcc=5.


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